IEICE Technical Committee Submission System
Conference Schedule		 Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 1 of 1  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
CAS, SIP, VLD 2007-06-22
11:30		 Hokkaido Hokkaido Tokai Univ. （Sapporo) Power Constrained IP Core Wrapper Design with Partitioned Clock Domains
Thomas Edison Yu, Tomokazu Yoneda (NAIST), Danella Zhao (Unive. of Louisiana), Hideo Fujiwara (NAIST) CAS2007-25 VLD2007-41 SIP2007-55		 Rapid developments in VLSI technology has made it possible to embed whole system components onto a single chip, called S... [more] CAS2007-25 VLD2007-41 SIP2007-55
pp.37-42
 Results 1 - 1 of 1  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan