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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
RECONF, CPSY, VLD, IPSJ-SLDM |
2008-01-16 15:10 |
Kanagawa |
Hiyoshi Campus, Keio University |
Development of verification and power estimation methodology for circuits with Run Time Power Gating Mitsutaka Nakata, Toshiaki Shirai, Toshihiro Kashima, Seidai Takeda, Kimiyoshi Usami (S.I.T.), Naomi Seki, Yohei Hasegawa, Hideharu Amano (Keio Univ.) VLD2007-111 CPSY2007-54 RECONF2007-57 |
When applying Run-Time Power Gating (RTPG) to a design,logic verification is one of the major problems.Gate-level simula... [more] |
VLD2007-111 CPSY2007-54 RECONF2007-57 pp.37-42 |
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