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Committee Date Time Place Paper Title / Authors Abstract Paper #
CAS, NLP 2013-09-26
12:40		 Gifu Satellite Campus, Gifu University Efficient Transient Analysis of 3-D Stacked On-Chip Power Distribution Network with Power/Ground Through Silicon Vias by Using Block Latency Insertion Method
Daisei Nagata, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) CAS2013-36 NLP2013-48		 In this report, we apply the block latency insertion method (block-LIM) to the transient analysis of on-chip power distr... [more] CAS2013-36 NLP2013-48
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