IEICE Technical Committee Submission System
Conference Schedule		 Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 5 of 5  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD 2012-03-07
14:35		 Oita B-con Plaza Performance of the Evaluation of a Variable-Latency-Circuit on FPGA
Yuuta Ukon, Kenta Ando, Atsushi Takahashi (Osaka Univ) VLD2011-141		 The performance of integrated circuits, which are the base of ICT nowaday,
is always requested to be improved.
In de f... [more]		 VLD2011-141
pp.127-132
VLD 2011-03-04
13:10		 Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center An evaluation of error detection/correction circuits by gate level simulation
Masafumi Inoue (Tokyo Tech.), Yuuta Ukon, Atsushi Takahashi (Osaka Univ.) VLD2010-141		 In a typical synchronous circuit design, the maximum delay between flip-flops gives a lower bound of the clock period su... [more] VLD2010-141
pp.147-152
VLD 2011-03-04
13:35		 Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center Behavior Verification of a Variable Latency Circuit on FPGA
Yuuta Ukon (Osaka Univ), Masafumi Inoue (Tokyo Tech), Atsushi Takahashi, Kenji Taniguchi (Osaka Univ) VLD2010-142		  [more] VLD2010-142
pp.153-158
VLD 2010-03-12
10:25		 Okinawa   Performance evaluation of ADDER with Error-Detection-Correction Mechanism
Yuuta Ukon (Osaka Univ), Masafumi Inoue (Tokyo Inst. of Tech.), Atsushi Takahashi, Kenji Taniguchi (Osaka Univ) VLD2009-121		 In complete-synchronous framework that is adopted as de facto standard in clock-synchronous circuit design, the maximum ... [more] VLD2009-121
pp.133-137
ICD 2009-12-14
13:30		 Shizuoka Shizuoka University (Hamamatsu) [Poster Presentation] An evaluation of delay error rate of an adder in terms of clock period
Yuuta Ukon, Atsushi Takahashi, Kenji Taniguchi (Osaka Univ.) ICD2009-91		 Currently, digital circuits are mainly realized as synchronous circuits that uses global clocks. In clock-synchronous ci... [more] ICD2009-91
pp.77-81
 Results 1 - 5 of 5  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan