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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 10:30 |
Kagoshima | On Synthesis Algorithm for Parallel Index Generator Units Yusuke Matsunaga (Kyushu Univ.)  VLD2013-88 DC2013-54 |
The index generation function is a multi-valued logic function which checks if the given input vector is a registered or... [more] | VLD2013-88 DC2013-54 pp.203-208 |
|
| SIP, CAS, MSS, VLD | 2013-07-11 17:40 |
Kumamoto | Kumamoto Univ. | An Area and Delay Efficient Implementation of The Index Generation Functions Yusuke Matsunaga (Kyushu Univ.) CAS2013-15 VLD2013-25 SIP2013-45 MSS2013-15 |
[more] | CAS2013-15 VLD2013-25 SIP2013-45 MSS2013-15 pp.77-82 |
| DC | 2013-02-13 10:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Accelerating techniques for SAT-based test pattern generation Yusuke Matsunaga (Kyushu Univ.) DC2012-81 |
A naive way to solve ATPG problem using SAT solver is to formulate a test generation problem for a fault at a time. Thi... [more] |
DC2012-81 pp.7-12 |
| DC | 2013-02-13 15:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An Evaluatoin Method of Test Compactors for Secure Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.) DC2012-87 |
[more] | DC2012-87 pp.43-47 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 14:15 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A novel efficient data structure representing shared DAG patterns Yusuke Matsunaga (Kyushu Univ.) VLD2012-86 DC2012-52 |
Technology mapping and local rewriting in logic synthesis use many small size DAG patterns. Even though they share the i... [more] | VLD2012-86 DC2012-52 pp.159-162 |
| VLD, CAS, MSS, SIP | 2012-07-02 14:10 |
Kyoto | Kyoto Research Park | An Evaluation of Heuristic Fault Simulation Algorithms for Transient Faults in Sequential Circuits Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.) CAS2012-10 VLD2012-20 SIP2012-42 MSS2012-10 |
[more] | CAS2012-10 VLD2012-20 SIP2012-42 MSS2012-10 pp.55-60 |
| VLD, CAS, MSS, SIP | 2012-07-02 14:50 |
Kyoto | Kyoto Research Park | On efficiently computing of indirect implications Yusuke Matsunaga (Kyushu Univ.) CAS2012-12 VLD2012-22 SIP2012-44 MSS2012-12 |
[more] | CAS2012-12 VLD2012-22 SIP2012-44 MSS2012-12 pp.67-72 |
| VLD | 2012-03-07 10:05 |
Oita | B-con Plaza | An Efficient Method to Analyze Logic Masking Effects of Soft Errors in Sequential Circuits Taiga Takata, Yusuke Matsunaga (Kyushu Univ.) VLD2011-134 |
[more] | VLD2011-134 pp.85-90 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-29 13:50 |
Miyazaki | NewWelCity Miyazaki | Ymtools: an infrastructure for research and development of logic synthesis and verification Yusuke Matsunaga (Kyushu Univ.) VLD2011-78 DC2011-54 |
[more] | VLD2011-78 DC2011-54 pp.153-158 |
| VLD | 2011-09-27 10:45 |
Fukushima | University of Aizu | A statistical evaluation of approximate methods for soft error tolerance analysis of combinational circuits Hidenori Ayabe, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.) VLD2011-49 |
An approximate method which evaluates soft error tolerance with sampling has been proposed. There is an method to evalua... [more] | VLD2011-49 pp.49-54 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-17 13:50 |
Kanagawa | Keio Univ (Hiyoshi Campus) | A Heuristic Method using CODCs for Extraction of Maximum Observability Don't Care Set Taiga Takata, Yusuke Matsunaga (Kyushu Univ.) VLD2010-91 CPSY2010-46 RECONF2010-60 |
Sets of observability don't cares (ODCs) can be employed for multi-level logic optimization or propagation analysis of p... [more] | VLD2010-91 CPSY2010-46 RECONF2010-60 pp.43-48 |
| VLD | 2010-09-28 15:50 |
Kyoto | Kyoto Institute of Technology | Modeling of Latching Probability of Soft-Error-Induced Pulse Motoharu Hirata, Masayoshi Yoshimura, Yusuke Matsunaga (Kyusyu Univ.) VLD2010-56 |
This paper describes soft error which is one of the dependability decrease factors of LSI(Large Scale Integrated circuit... [more] | VLD2010-56 pp.83-88 |
| VLD, IPSJ-SLDM | 2010-05-19 16:10 |
Fukuoka | Kitakyushu International Conference Center | Highly Accurate Approximate Methods for Soft Error Tolerance Estimation for Sequential Circuits Naoki Shirobayashi, Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.) VLD2010-2 |
Soft error tolerance estimation method is necessary for soft error aware logic designs. There is an exact method has b... [more] |
VLD2010-2 pp.25-30 |
| VLD, IPSJ-SLDM | 2010-05-19 16:35 |
Fukuoka | Kitakyushu International Conference Center | An Approximate Method for Steady State Probability Calculation based on FSM Splitting So Hasegawa, Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.) VLD2010-3 |
An exact method evaluate soft error tolerance with Markov model has been proposed. This method, however, is difficult t... [more] |
VLD2010-3 pp.31-36 |
| VLD | 2010-03-12 13:55 |
Okinawa | An Acceleration of Soft Error Torelance Estimation Method for Sequential Circuits by Reducing the Number of States Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.) VLD2009-126 |
Soft error tolerance estimation method is necessary for the soft error aware logic design. We proposed an estimation met... [more] | VLD2009-126 pp.163-168 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-03 10:00 |
Kochi | Kochi City Culture-Plaza | An Evaluation of Approximate Methods for Soft Error Tolerance Evaluation of Sequential Circuits Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.) VLD2009-49 DC2009-36 |
Soft error tolerance evaluation method is necessary for the soft error aware logic design. An evaluation method with Mar... [more] | VLD2009-49 DC2009-36 pp.55-60 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-04 15:40 |
Kochi | Kochi City Culture-Plaza | FlexMerge: A Logic Optimization Technique to Minimize Area for LUT-based FPGAs Taiga Takata, Yusuke Matsunaga (Kyushu Univ.) VLD2009-68 DC2009-55 |
This paper presents a novel logic optimization technique to minimize the number of LUTs for the post-processing of LUT-b... [more] | VLD2009-68 DC2009-55 pp.185-190 |
| VLD | 2009-09-24 15:50 |
Osaka | Osaka University | On accelleration of SER analysis for sequential circuits using implicit enumeration Yusuke Matsunaga, Yusuke Akamine (Kyushu Univ.) VLD2009-34 |
[more] | VLD2009-34 pp.31-36 |
| DC, CPSY | 2009-04-21 13:50 |
Tokyo | Akihabara Satellite Campus, Tokyo Metropolitan Univ. | Fast Soft Error Rate Estimation for Circuits Containing Arithmetic Units Motoharu Hirata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura (Kyushu Univ.) CPSY2009-5 DC2009-5 |
This paper describes soft errors which are errors in LSI that are due to external radiation.The soft error rate (SER) wh... [more] | CPSY2009-5 DC2009-5 pp.25-30 |
| DC, CPSY | 2009-04-21 16:10 |
Tokyo | Akihabara Satellite Campus, Tokyo Metropolitan Univ. | Pulse Generation Analysis for SER Estimation Targeted to Cell-based Design. Daisuke Kozuwa, Masayoshi Yoshimura, Yusuke Matsunaga (Kyusyu Univ.) CPSY2009-8 DC2009-8 |
The charge deposition that results from a neutron strikes to a transistor alter the memory state or the logic state of o... [more] | CPSY2009-8 DC2009-8 pp.43-48 |
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