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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD | 2016-03-02 11:20 |
Okinawa | Okinawa Seinen Kaikan | Performance Improvement by Engineering Change Order in General-Synchronous Framework for Altera FPGA Hayato Mashiko, Takuya Oba, Yukihide Kohira (Univ. of Aizu)  VLD2015-137 |
Recently, the logic circuits are implemented to FPGA instead of ASIC in many fields. However, the circuit implemented to... [more] | VLD2015-137 pp.149-154 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 16:20 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Formulation to SAT for Acceleration in 1D Layout Area Minimization of CMOS circuits Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) VLD2015-51 DC2015-47 |
In layout design for LSI circuits, the layout area is minimized to reduce the fabrication cost and to increase the yield... [more] | VLD2015-51 DC2015-47 pp.81-86 |
| VLD | 2015-03-02 15:20 |
Okinawa | Okinawa Seinen Kaikan | Area Minimization of One-Dimensional Layout for MOS Circuits by SAT Solver and Simulated Annealing Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) VLD2014-158 |
[more] | VLD2014-158 pp.31-36 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 11:10 |
Oita | B-ConPlaza | Technology Mapping Method for Low Power Consumption and High Performance in General-Synchronous Framework Junki Kawaguchi, Yukihide Kohira (Univ. of Aizu) VLD2014-83 DC2014-37 |
In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily si... [more] | VLD2014-83 DC2014-37 pp.87-92 |
| RCC, ASN, NS, RCS, SR (Joint) |
2014-07-31 10:50 |
Kyoto | Kyoto Terrsa | [Poster Presentation]
Development of a Sensor Network to Measure Snow Depth using Arduino Shunya Hosaka, Yosuke Moriai, Masamitsu Nakajima, Yukihide Kohira, Hiroshi Saito (Univ. Aizu) RCC2014-26 NS2014-46 RCS2014-98 SR2014-27 ASN2014-45 |
To reduce accident, traffic and economic paralysis, and effect for personal life caused by snow, we develop a sensor net... [more] | RCC2014-26 NS2014-46 RCS2014-98 SR2014-27 ASN2014-45 pp.23-28(RCC), pp.1-6(NS), pp.55-60(RCS), pp.43-48(SR), pp.31-36(ASN) |
| VLD, IPSJ-SLDM | 2014-05-29 11:30 |
Fukuoka | Kitakyushu International Conference Center | LELECUT Triple Patterning Lithography Layout Decomposition using Positive Semidefinite Relaxation Yukihide Kohira (Univ. of Aizu), Tomomi Matsui (Tokyo Tech), Yoko Yokoyama, Chikaaki Kodama (Toshiba), Atsushi Takahashi (Tokyo Tech), Shigeki Nojima, Satoshi Tanaka (Toshiba) VLD2014-6 |
One of the most promising techniques in the 14 nm logic node and beyond is triple patterning lithography (TPL). Recently... [more] | VLD2014-6 pp.27-32 |
| VLD | 2014-03-04 13:50 |
Okinawa | Okinawa Seinen Kaikan | Local Pattern Modification Method for Lithographical ECO in Double Patterning Yutaro Miyabe, Atsushi Takahashi, Tomomi Matsui (Tokyo Inst. of Tech.), Yukihide Kohira (Univ. of Aizu), Yoko Yokoyama (Toshiba) VLD2013-149 |
In advanced semiconductor manufacturing processes, even though a pattern is generated according to a design rule, hot s... [more] |
VLD2013-149 pp.87-92 |
| VLD | 2014-03-05 16:10 |
Okinawa | Okinawa Seinen Kaikan | Implementation of General-Synchronous Circuits into FPGA using Multi-Domain Clock Skew Scheduling Tatsuya Masui, Yukihide Kohira (Univ. of Aizu) VLD2013-167 |
Recently, instead of implementation into ASIC, implementation into FPGA is used in many fields. However, in general, cir... [more] | VLD2013-167 pp.183-188 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 13:45 |
Kagoshima | A Tuning Method of Programmable Delay Element with an Ordered Finite Set of Delay Values for Yield Improvement Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) VLD2013-99 DC2013-65 |
Due to progressing the process technology in LSI, the yield of LSI chips is reduced by timing violations caused by delay... [more] | VLD2013-99 DC2013-65 pp.275-280 |
|
| VLD, IPSJ-SLDM | 2013-05-16 09:50 |
Fukuoka | Kitakyushu International Conference Center | A Longest Path Algorithm for Differential Pair Net Considering Connectivity Koji Yamazaki, Yukihide Kohira (Univ. of Aizu) VLD2013-3 |
In recent years, due to the speedup and miniaturization in LSI systems, PCB routing design uses many differential pair n... [more] | VLD2013-3 pp.13-18 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-26 16:50 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Delay Tuning Method of Programmable Delay Element with Two Delay Values for Yield Improvement Hayato Mashiko, Yukihide Kohira (UoA) VLD2012-69 DC2012-35 |
Due to progressing the process technology in LSI and increasing delay variations of interconnection and gate delays afte... [more] | VLD2012-69 DC2012-35 pp.57-62 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 09:25 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | An Acceleration Method by GPGPU for Analytical Placement using Quasi-Newton Method Yukihide Kohira (UoA), Yasuhiro Takashima (Univ. of Kitakyushu) VLD2012-74 DC2012-40 |
In this paper, we propose an acceleration method by GPGPU for an analytical placement method using a quasi-Newton method... [more] | VLD2012-74 DC2012-40 pp.87-92 |
| VLD | 2012-03-06 16:20 |
Oita | B-con Plaza | A Length Matching Routing Algorithm on Single Layer Using Longer Path Algorithm for Single Net Syouhei Furuyama, Yukihide Kohira (UoA) VLD2011-131 |
Due to the increase of operation frequency in recent LSI systems, signal propagation delays are required to achieve spec... [more] | VLD2011-131 pp.67-72 |
| IPSJ-SLDM, VLD | 2011-05-18 14:40 |
Fukuoka | Kitakyushu International Conference Center | An Effective Overlap Removable Objective for Analytical Placement Syota Kuwabara, Yukihide Kohira (Univ. of Aizu), Yasuhiro Takashima (Univ. of Kitakyushu) VLD2011-2 |
In the recent LSI design, it is difficult to obtain the placement which satisfies design constraints and specifications ... [more] | VLD2011-2 pp.7-12 |
| VLD | 2010-09-27 17:00 |
Kyoto | Kyoto Institute of Technology | [Invited Talk]
Length Matching Routing on Single Layer for PCB Routing Design Yukihide Kohira (UoA), Atsushi Takahashi (Osaka Univ.) VLD2010-47 |
Due to the increase of operation frequency in recent LSI systems, signal propagation delays are required to achieve spec... [more] | VLD2010-47 pp.31-36 |
| VLD, IPSJ-SLDM | 2010-05-20 13:55 |
Fukuoka | Kitakyushu International Conference Center | An Efficient Congested Area Specification And Congestion Relaxation by 45 Degree Line for Single Layer Printed Circuit Board Rouitng Kyosuke Shinoda (Tokyo Tech), Yukihide Kohira (UoA), Atsushi Takahashi (Osaka Univ.) VLD2010-9 |
In recent VLSI systems, system performance increases while system size reduces. In Printed Circuit Board (PCB) design, ... [more] |
VLD2010-9 pp.79-84 |
| VLD | 2010-03-11 15:00 |
Okinawa | Fast Estimation Method of Peak Power considered Input Vector and Inner State of a Circuit Nobuyoshi Takahashi (Tokyo Inst. of Tech.), Yoichi Tomioka (Tokyo Univ. of Agriculture and Tech.), Yukihide Kohira (The Univ. of Aizu), Atsushi Takahashi (Osaka Univ.) VLD2009-115 |
The peak power of a clock synchronous circuit is requested to be small to reduce the influence on circuit performance an... [more] | VLD2009-115 pp.97-102 |
|
| VLD | 2010-03-11 16:55 |
Okinawa | Clustering Method for Low Power Clock Tree in General Syncrhonous Framework Yukihide Kohira (Univ. of Aizu), Atsushi Takahashi (Osaka univ) VLD2009-119 |
In general synchronous framework, in which the clock is not assumed to be distributed to all registers simultaneously, t... [more] | VLD2009-119 pp.121-126 |
|
| VLD | 2009-09-24 14:20 |
Osaka | Osaka University | A Wall Generation for Trunk Routing of Multiple Nets on Single Layer Yukihide Kohira (Univ. of Aizu.), Atsushi Takahashi (Osaka Univ.) VLD2009-31 |
In this paper, we propose a wall generation for trunk routing of multiple nets on single layer. An existing routing meth... [more] | VLD2009-31 pp.13-18 |
| SIP, CAS, VLD | 2009-07-02 13:30 |
Hokkaido | Kushiko-shi Shogai Gakushu Center | Octilinear Routing Method with Congestion Relaxation by Slant Lines Kyosuke Shinoda (Tokyo Tech), Yukihide Kohira (UoA), Atsushi Takahashi (Osaka Univ.) CAS2009-18 VLD2009-23 SIP2009-35 |
In recent Printed Circuit Boards (PCB), the design size and density are increased, and the improvement of routing tools ... [more] | CAS2009-18 VLD2009-23 SIP2009-35 pp.97-102 |
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