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Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF 2023-09-15
14:15		 Tokyo Tokyo University of Agriculture and Technology Koganei campus
(Primary: On-site, Secondary: Online)		 Library Development for RISC-V FPGA SoCs
Takuya Kojima (UTokyo/JST PRESTO), Yosuke Yanai (Keio Univ.), Hayate Okuhara (NUS), Hideharu Amano (Keio Univ.), Morihiro Kuga, Masahiro Iida (Kumamoto Univ.) RECONF2023-31		  [more] RECONF2023-31
pp.52-57
CPSY, DC, IPSJ-ARC [detail] 2023-08-04
18:20		 Hokkaido Hakodate Arena
(Primary: On-site, Secondary: Online)		 Power Evaluation of "SLMLET" Chip with Mixed RISC-V MP and SLM Reconfiguration Logic
Yosuke Yanai (Keio Univ.), Takuya Kojima (Tokyo Univ./JST PRESTO), Hayate Okuhara (NUS), Hideharu Amano (Keio Univ.), Morihiro Kuga, Masahiro Iida (Kumamoto Univ.) CPSY2023-25 DC2023-25		 In recent years, opportunities requiring processing at the IoT edge have been increasing. As a solution, not only conven... [more] CPSY2023-25 DC2023-25
pp.100-105
CPSY, DC, IPSJ-ARC [detail] 2022-07-28
13:30		 Yamaguchi Kaikyo Messe Shimonoseki
(Primary: On-site, Secondary: Online)		 Preliminary evaluation of "SLMLET" chip with RISC-V MP and SLM reconfigurable logic
Yosuke Yanai (Keio Univ.), Takuya Kojima (Tokyo Univ.), Hayate Okuhara (NUS.), Hideharu Amano (Keio Univ.), Masahiro Iida (Kumamoto Univ.) CPSY2022-8 DC2022-8		 In recent years, processing power in IoT edge devices has been further improved. Therefore, a solution called a mixed FP... [more] CPSY2022-8 DC2022-8
pp.41-46
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2022-03-10
14:30		 Online Online Compression of configuration data in Scalable Logic Module
Souhei Takagi, Naoya Niwa, Yoshiya Shikama, Yosuke Yanai, Hideharu Amano (Keio Univ), Yuya Nakasato, Daiki Amagasaki, Masahiro Iida (Kumamoto Univ) CPSY2021-49 DC2021-83		 (To be available after the conference date) [more] CPSY2021-49 DC2021-83
pp.26-31
CPSY, DC, IPSJ-ARC
(Joint) [detail]		 2018-07-30
14:30		 Kumamoto Kumamoto City International Center Proposition and Implementation of RISC-V Processor with Data path extension for 10G Ethernet
Yosuke Yanai, Takeshi Matsuya, Yohei Kuga, Tokusashi Yuta, Jun Murai (Keio Univ.) CPSY2018-15		 In this paper, we propose a processor with 1024 bit wide data path for packet processing. A software packet processing e... [more] CPSY2018-15
pp.33-38
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