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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF | 2011-09-26 10:45 |
Aichi | Nagoya Univ. | Wavepipelining on A Ultra Low Power Reconfigurable Accelerator CMA-1. Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. of Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (The Univ. of Electro-Communications)  RECONF2011-22 |
CMA(Cool Mega-Array)-1 is a prototype media accelerator consisting of a large PE array which includes 24bit 8 × 8 PEs wi... [more] | RECONF2011-22 pp.1-6 |
| RECONF | 2011-05-13 10:45 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Optimization of Application Programs of SLD-1 : A Low Power Accelarator Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Tech. Univ.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Tokyo Univ. of Electro-Communication) RECONF2011-15 |
SLD(Silent Large Datapath)-1 is a prototype media accelerator consisting of a large PE array which includes 24bit 8 × 8 ... [more] | RECONF2011-15 pp.85-90 |
| RECONF | 2011-05-13 11:10 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Implementation and Evaluation of a low power accelerator SLD-2 Mai Izawa, Nobuaki Ozaki, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano (Keio Univ.) RECONF2011-16 |
Silent Large Datapath or SLD is a novel high performance but low power accelerator architecture for battery driven mobil... [more] | RECONF2011-16 pp.91-96 |
| SWIM | 2011-02-25 15:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Verifying UML Inter-Model Consistency Using CPN Masato Nomura, Yoshihiro Yasuda, Yoshiyuki Shinkawa (Ryukoku Univ.) SWIM2010-31 |
UML state machine diagrams, sequence diagrams, and activity diagrams are often used in combination together to model the... [more] | SWIM2010-31 pp.33-38 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 14:50 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Silent Large Datapath : A Ultra Low Power Accelarater Yoshihiro Yasuda, Nobuaki Ozaki, Masayuki Kimura, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Univ. of Electro-Communications) VLD2010-109 CPSY2010-64 RECONF2010-78 |
Silent Large Datapath (SLD) is a low power reconfigurable accelerator for high performance embedded systems. By using a... [more] |
VLD2010-109 CPSY2010-64 RECONF2010-78 pp.169-174 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 15:10 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Real Chip evaluation of Silent Large Datapath:A Ultra Low Power Accelarater Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Univ. of Electro-Communications) VLD2010-110 CPSY2010-65 RECONF2010-79 |
Battery driven multi-media applications require both high performance and energy efficiency. Recon-figurable... [more] | VLD2010-110 CPSY2010-65 RECONF2010-79 pp.175-180 |
| SWIM | 2010-11-19 15:25 |
Tokyo | Tokai Univ. Takanawa Campus(Tokyo) | Verification of UML Sequence Diagrams with Time Constraints Yoshihiro Yasuda, Yoshiyuki Shinkawa (Ryukoku Univ.) SWIM2010-23 |
Verification of the system specification is usually performed independently from three major different viewpoints, that ... [more] | SWIM2010-23 pp.39-44 |
| SWIM | 2010-02-26 16:25 |
Tokyo | Kikai Sinkukaikan B3-2 | Description and Verification of Time Constrains in UML Sequence Diagrams Yoshihiro Yasuda, Yoshiyuki Shinkawa (Ryukoku Univ.) SWIM2009-24 |
In UML 2.0, it is possible to describe time constraints in sequence diagrams. However it seems difficult to validate or ... [more] | SWIM2009-24 pp.27-32 |
| RECONF | 2009-05-14 13:30 |
Fukui | Real Chip Evaluation of Dynamically Reconfigurable Processor Array MuCCRA-3 Yoshihiro Yasuda, Yoshiki Saito, Toru Sano, Masaru Kato, Hideharu Amano (Keio Univ.) RECONF2009-2 |
Dynamically Reconfigurable Processor Array(DRPA) has been received an attention as a flexible and power efficient off-lo... [more] | RECONF2009-2 pp.7-12 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 13:50 |
Fukuoka | Kitakyushu Science and Research Park | Preliminary Evaluations of SMA: A Massive Array of Low-Power Reconfigurable Processors Hideharu Amano (Keio Univ.), Kyundong Kim (Tokyo Univ.), Hiroki Matsutani, Vasutan Tunbungheng, Yoshihiro Yasuda (Keio Univ.), Masaaki Kondo (The University of Electro-Communications), Hiroshi Nakamura (Tokyo Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.) RECONF2008-40 |
SMA (Silent Mega Array) is a highly energy efficient coarse-grained reconfigurable system. By mapping a data-flow grap... [more] |
RECONF2008-40 pp.9-14 |
| RCS, AP (Joint) |
2007-11-08 13:30 |
Tokyo | Univ. of Electro-Commun. | Interferometric Observation of Over-horizon VHF Signals Associated with Earthquakes Yoshihiro Yasuda (Univ. of Electro-Communications), Takeyoshi Gotoh (Yokogawa Electric Corporation), Yuichi Ida, Naoyuki Yonaiguchi, Masashi Hayakawa (Univ. of Electro-Communications) AP2007-109 |
[more] | AP2007-109 pp.41-46 |
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