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Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF 2009-09-18
09:00
Tochigi Utsunomiya Univ. A Proposal for a Method to Generate Optimized Dataflow for Reconfigurable Processor DS-HIE Based on Bit Serial Operation
Yasuhiro Nishinaga, Ken'ichi Umeda, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) RECONF2009-28
Our laboratory has developed a reconfigurable processor DS-HIE based on bit-serial operation. The DS-HIE processor achie... [more] RECONF2009-28
pp.55-60
RECONF 2009-09-18
09:25
Tochigi Utsunomiya Univ. Consideration of Data Transfer Unit in Reconfigurable Processor DS-HIE
Ken'ichi Umeda, Yasuhiro Nishinaga, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ) RECONF2009-29
We have developed reconfigurable processor DS-HIE based on bit-serial operation. The merit of bit-serial operation is th... [more] RECONF2009-29
pp.61-66
RECONF 2008-05-22
14:50
Fukushima The University of Aizu Development of Compiler for Dynamic Reconfigurable Architecture DS-HIE which Adopts Digit-serial Computation
Yasuhiro Nishinaga, Takuro Uchida, Tetsuya Zuyama, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) RECONF2008-5
In our laboratory, to realize speedup of the streaming processing for small scale systems such as embeded systems, we ha... [more] RECONF2008-5
pp.25-30
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