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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM, ICD, ITE-IST [detail] | 2017-08-01 09:00 |
Hokkaido | Hokkaido-Univ. Multimedia Education Bldg. | [Invited Talk]
A Nonvolatile SRAM Integrated with Ferroelectric HfO2 Capacitor for Normally-Off Operation Masaharu Kobayashi, Nozomu Ueyama, Toshiro Hiramoto (Univ. of Tokyo)  SDM2017-37 ICD2017-25 |
[more] | SDM2017-37 ICD2017-25 pp.45-48 |
| SDM, ICD, ITE-IST [detail] | 2017-08-01 09:45 |
Hokkaido | Hokkaido-Univ. Multimedia Education Bldg. | Parallel Programming of Non-volatile Power-up States of SRAM Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya (Univ. of Tokyo), Hirofumi Shinohara (Waseda Univ.), Masaharu Kobayashi, Toshiro Hiramoto (Univ. of Tokyo) SDM2017-38 ICD2017-26 |
A technique for using an ordinary SRAM array for programmable and readable non-volatile (NV) memory is proposed. Paralle... [more] | SDM2017-38 ICD2017-26 pp.49-54 |
| ICD, CPM, ED, EID, EMD, MRIS, OME, SCE, SDM, QIT (Joint) [detail] |
2017-01-31 10:55 |
Hiroshima | Miyajima-Morino-Yado(Hiroshima) | [Invited Talk]
Experimental Study on Operation Speed of Negative Capacitance FET with Ferroelectric HfO2 Masaharu Kobayashi, Nozomu Ueyama, Kyungmin Jang, Toshiro Hiramoto (IIS, Univ. of Tokyo) EMD2016-79 MR2016-51 SCE2016-57 EID2016-58 ED2016-122 CPM2016-123 SDM2016-122 ICD2016-110 OME2016-91 |
[more] | EMD2016-79 MR2016-51 SCE2016-57 EID2016-58 ED2016-122 CPM2016-123 SDM2016-122 ICD2016-110 OME2016-91 pp.51-54 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 10:30 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | [Invited Talk]
Development of Three-Dimensional Integrated CMOS Image Sensors with Pixel-Parallel Signal Processors by Using Direct Bonding of SOI Layers Masahide Goto, Yuki Honda, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi (NHK), Takuya Saraya, Masaharu Kobayashi, Eiji Higurasgi, Hiroshi Toshiyoshi, Toshiro Hiramoto (Univ. Tokyo) CPM2016-79 ICD2016-40 IE2016-74 |
[more] | CPM2016-79 ICD2016-40 IE2016-74 pp.17-21 |
| SDM | 2016-10-26 15:30 |
Miyagi | Niche, Tohoku Univ. | [Invited Talk]
Back-Bias Control Technique for Suppression of Die-to-Die Delay Variability of SOTB CMOS Circuits at Ultralow-Voltage (0.4 V) Operation Hideki Makiyama, Yoshiki Yamamoto, Takumi Hasegawa, Shinobu Okanishi, Keiichi Maekawa, Hiroki Shinkawata, Shiro Kamohara, Yasuo Yamaguchi (Renesas Electronics Corp.), Nobuyuki Sugii (Hitach), Koichiro Ishibashi (The Univ. of Electro-Communications), Tomoko Mizutani, Toshiro Hiramoto (The Univ. of Tokyo) SDM2016-71 |
Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation volta... [more] | SDM2016-71 pp.15-20 |
| ICD, SDM, ITE-IST [detail] | 2016-08-03 15:05 |
Osaka | Central Electric Club | Increased Drain-Induced Variability and Within-Device Variability in Extremely Narrow Silicon Nanowire MOSFETs with Width down to 2nm Tomoko Mizutani, Kiyoshi Takeuchi, Ryota Suzuki, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto (Univ. of Tokyo) SDM2016-67 ICD2016-35 |
The effects of drain voltage in threshold voltage variability in extremely narrow silicon nanowire (NW) channel FETs are... [more] | SDM2016-67 ICD2016-35 pp.123-126 |
| ICD, SDM, ITE-IST [detail] | 2016-08-03 15:30 |
Osaka | Central Electric Club | Performance Enhancement of Tunnel FET by Negative Capacitance Masaharu Kobayashi, Kyungmin Jang, Nozomu Ueyama, Toshiro Hiramoto (Univ. of Tokyo) SDM2016-68 ICD2016-36 |
IoT devices in a sensor network require a new energy-efficient transistor which operates at ultralow voltage and power e... [more] | SDM2016-68 ICD2016-36 pp.127-130 |
| SDM, ICD | 2015-08-24 11:45 |
Kumamoto | Kumamoto City | [Invited Talk]
Device Design Guideline for negative capacitance FET (NCFET) Masaharu Kobayashi, Toshiro Hiramoto (The Univ. of Tokyo) SDM2015-60 ICD2015-29 |
[more] | SDM2015-60 ICD2015-29 pp.15-18 |
| SDM, ICD | 2015-08-25 10:55 |
Kumamoto | Kumamoto City | [Invited Talk]
Novel Single p+Poly-Si/Hf/SiON Gate Stack Technology on Silicon-on-Thin-Buried-Oxide (SOTB) for Ultra-Low Leakage Applications Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Yasuo Yamaguchi (Renesas Electronics Corp.), Nobuyuki Sugii (Hitachi), Tomoko Mizutani, Masaharu Kobayashi, Toshiro Hiramoto (UT) SDM2015-67 ICD2015-36 |
We demonstrate a cost effective 65-nm SOTB CMOS technology for ultra-low leakage applications. Novel single p+poly-Si/Hf... [more] | SDM2015-67 ICD2015-36 pp.53-57 |
| SDM, ICD | 2015-08-25 11:45 |
Kumamoto | Kumamoto City | Threshold Voltage and Current Variability of Extremely Narrow Silicon Nanowire MOSFETs with Width down to 2nm Tomoko Mizutani, Yuma Tanahashi, Ryota Suzuki, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto (Univ. of Tokyo) SDM2015-68 ICD2015-37 |
[more] | SDM2015-68 ICD2015-37 pp.59-62 |
| SDM | 2015-01-27 14:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Three-Dimensional Integrated CMOS Image Sensors with Pixel-Parallel A/D Converters Fabricated by Direct Bonding of SOI Layers Masahide Goto, Kei Hagiwara, Yoshinori Iguchi, Hiroshi Ohtake (NHK), Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto (The Univ. of Tokyo) SDM2014-141 |
We report the first demonstration of three-dimensional (3D) integrated CMOS image sensors with pixel-parallel A/D conver... [more] | SDM2014-141 pp.25-28 |
| SDM | 2014-10-17 14:30 |
Miyagi | Niche, Tohoku Univ. | [Invited Talk]
Back-Bias Control technique for Suppression of Die-to-Die Delay Variability of SOTB MOS Circuits at Ultralow-Voltage (0.4 V) Operation Hideki Makiyama, Yoshiki Yamamoto, Hidekazu Oda, Shiro Kamohara, Nobuyuki Sugii, Yasuo Yamaguchi (LEAP), Koichiro Ishibashi (Univ. of Electro-Communications), Tomoko Mizutani, Toshiro Hiramoto (Univ. of Tokyo) SDM2014-94 |
Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation volta... [more] | SDM2014-94 pp.61-68 |
| ICD, SDM | 2014-08-05 09:00 |
Hokkaido | Hokkaido Univ., Multimedia Education Bldg. | [Invited Talk]
Ultra-Low Voltage (0.1V) Operation of Threshold Voltage Self-Adjusting MOSFET and SRAM Cell Toshiro Hiramoto, Akitsugu Ueda, Seung-Min Jung, Tomoko Mizutani, Takuya Saraya (Univ. of Tokyo) SDM2014-71 ICD2014-40 |
A new Vth self-adjusting MOSFET operating at 0.1V is proposed, where Vth automatically decreases at on-state and increas... [more] | SDM2014-71 ICD2014-40 pp.51-54 |
| ICD, SDM | 2014-08-05 09:50 |
Hokkaido | Hokkaido Univ., Multimedia Education Bldg. | Statistical Analysis of Minimum Operation Voltage (Vmin) in Fully Depleted Silicon-on-Thin-BOX (SOTB) SRAM Cells Tomoko Mizutani (Univ. of Tokyo), Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Nobuyuki Sugii (LEAP), Toshiro Hiramoto (Univ. of Tokyo) SDM2014-72 ICD2014-41 |
The minimum operation voltage (Vmin) of fully depleted (FD) silicon-on-thin-BOX (SOTB) SRAM cells are measured and stati... [more] | SDM2014-72 ICD2014-41 pp.55-58 |
| ICD | 2014-04-18 09:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Lecture]
Ultralow-Voltage Operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM Down to 0.37 V Utilizing Adaptive Back Bias Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Nobuyuki Sugii, Yasuo Yamaguchi (LEAP), Tomoko Mizutani, Toshiro Hiramoto (UTokyo) ICD2014-11 |
We demonstrated record 0.37V minimum operation voltage (VMIN) of 2Mb Silicon-on-Thin-Buried-oxide (SOTB) 6T-SRAM. Thanks... [more] | ICD2014-11 pp.53-57 |
| SDM | 2014-01-29 13:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Analysis of Transistor Characteristics in Distribution Tails beyond ±5.4σ of 11 Billion Transistors Tomoko Mizutani, Anil Kumar, Toshiro Hiramoto (Univ. of Tokyo) SDM2013-142 |
Transistors in distribution tails of 11G (11 billion) transistors were intensively measured and compared with transistor... [more] | SDM2013-142 pp.31-34 |
| SDM | 2014-01-29 14:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Suppression of Die-to-Die Delay Variability of Silicon on Thin Buried Oxide (SOTB) CMOS Circuits by Balanced P/N Drivability Control with Back-Bias for Ultralow-Voltage (0.4 V) Operation Hideki Makiyama, Yoshiki Yamamoto, Hirofumi Shinohara, Toshiaki Iwamatsu, Hidekazu Oda, Nobuyuki Sugii (LEAP), Koichiro Ishibashi (Univ. of Electro- Comm.), Tomoko Mizutani, Toshiro Hiramoto (Univ. of Tokyo), Yasuo Yamaguchi (LEAP) SDM2013-143 |
Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation volta... [more] | SDM2013-143 pp.35-38 |
| SDM, ICD | 2013-08-02 09:00 |
Ishikawa | Kanazawa University | SRAM Cell Stability Parameter: Noise Margin or Vmin? Anil Kumar, Takuya Saraya (Univ. of Tokyo), Shinji Miyano (STARC), Toshiro Hiramoto (Univ. of Tokyo) SDM2013-74 ICD2013-56 |
This paper reports the comprehensive analysis of the stability parameter of SRAM cells. Results show that even if noise ... [more] | SDM2013-74 ICD2013-56 pp.43-46 |
| SDM, ICD | 2013-08-02 09:25 |
Ishikawa | Kanazawa University | Reduced Cell Current Variability in Fully Depleted Silicon-on-Thin-BOX (SOTB) SRAM Cells at Supply Voltage of 0.4V Tomoko Mizutani (Univ. of Tokyo), Yoshiki Yamamoto, Hideki Makiyama, Hirofumi Shinohara, Toshiaki Iwamatsu, Hidekazu Oda, Nobuyuki Sugii (LEAP), Toshiro Hiramoto (Univ. of Tokyo) SDM2013-75 ICD2013-57 |
Cell current (ICELL) variability in 6T-SRAM composed of silicon-on-thin-BOX (SOTB) MOSFETs by 65nm technology is measure... [more] | SDM2013-75 ICD2013-57 pp.47-52 |
| SDM, ED | 2013-02-28 09:00 |
Hokkaido | Hokkaido Univ. | Integration of CMOS 1-bit Analog Selector and Single-Electron Transistors Operating at Room Temperature Ryota Suzuki, Motoki Nozue, Takuya Saraya, Toshiro Hiramoto (Univ. of Tokyo) ED2012-137 SDM2012-166 |
In this paper, integrated circuit operation of CMOS analog selector circuits and silicon single-electron transistors is ... [more] | ED2012-137 SDM2012-166 pp.47-52 |
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