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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 22  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2018-02-20
14:25
Tokyo Kikai-Shinko-Kaikan Bldg. A Golden-Free Hardware Trojan Detection Technique Considering Intra-Die Variation
Fakir Sharif Hossain, Tomokazu Yoneda, Michihiro Shintani, Michiko Inoue (NAIST), Alex Orailoglu (Univ. of California, San Diego) DC2017-84
High detection sensitivity in the presence of process variation is a key challenge for hardware Trojan detection through... [more] DC2017-84
pp.43-48
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-30
11:45
Osaka Ritsumeikan University, Osaka Ibaraki Campus A Golden-IC Free Clock Tree Driven Authentication Approach for Hardware Trojan Detection
Fakir Sharif Hossain, Tomokazu Yoneda, Michiko Inoue (NAIST), Alex Orailoglu (UCSD) VLD2016-67 DC2016-61
Due to outsourcing of numerous stages of the IC manufacturing process in different foundries, security risks such as har... [more] VLD2016-67 DC2016-61
pp.135-140
DC 2016-02-17
11:55
Tokyo Kikai-Shinko-Kaikan Bldg. Delay fault injection framework based on logic simulation with zero delay model
Shinji Kawasaki, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue (NAIST) DC2015-90
Fault injection is a technique to re-create faulty behavior of circuits and widely accepted method to evaluate soft erro... [more] DC2015-90
pp.25-30
DC 2016-02-17
14:25
Tokyo Kikai-Shinko-Kaikan Bldg. Built-In Self-Test with Combination of Weighted Random Pattern and Reseeding
Sayaka Satonaka, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue (NAIST) DC2015-92
Built-In Self-Test (BIST) is widely used to reduce test cost. However, it is difficult to achieve high fault coverage wi... [more] DC2015-92
pp.37-42
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-01
12:45
Nagasaki Nagasaki Kinro Fukushi Kaikan Scan Segmentation Approach to Magnify Detection Sensitivity for Tiny Hardware Trojan
Fakir Sharif Hossain, Tomokazu Yoneda, Michiko Inoue (NAIST) VLD2015-38 DC2015-34
Outsourcing of IC fabrication components has initiated the potential threat of design tempering using hardware Trojans ... [more] VLD2015-38 DC2015-34
pp.1-6
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-01
13:50
Nagasaki Nagasaki Kinro Fukushi Kaikan Background Sequence Generation for Neighborhood Pattern Sensitive Fault Testing in Random Access Memories
Shin'ya Ueoka, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue (NAIST) VLD2015-40 DC2015-36
The Neighborhood Pattern Sensitive Fault (NPSF) is widely discussed fault model for memories, and it occurs when a memor... [more] VLD2015-40 DC2015-36
pp.19-24
DC 2014-12-19
14:15
Toyama   Reliability of ECC-based Memory Architectures with Online Self-repair Capabilities
Gian Mayuga, Yuta Yamato, Tomokazu Yoneda (NAIST), Yasuo Sato (Kyutech), Michiko Inoue (NAIST) DC2014-70
 [more] DC2014-70
pp.19-24
DC 2013-12-13
13:00
Ishikawa   Efficient Scan-Based BIST Architecture for Application-Dependent FPGA Test
Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue (NAIST) DC2013-68
This paper presents a scan-based BIST architecture for testing of application-dependent circuits configured on FPGA.
I... [more]
DC2013-68
pp.1-6
DC 2013-02-13
16:40
Tokyo Kikai-Shinko-Kaikan Bldg. Data volume reduction method for unknown value handling in built-in self test used in field
Yuta Yoshimi (NAIST), Kazumi Hatayama, Yuta Yamato, Tomokazu Yoneda, Michiko Inoue (NAIST/JST) DC2012-90
Many approaches on test pattern compression targeted unknown value handling. It is because unknown values have impacts o... [more] DC2012-90
pp.61-66
DC 2012-06-22
16:10
Tokyo Room B3-1 Kikai-Shinko-Kaikan Bldg On Per-Cell Dynamic IR-Drop Estimation in At-Speed Scan Testing
Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue (NAIST) DC2012-15
It is well known that dynamic IR-drop analysis consumes large amount of time even for a few clock cycles. This paper add... [more] DC2012-15
pp.39-44
DC 2012-02-13
15:55
Tokyo Kikai-Shinko-Kaikan Bldg. Dynamic Test Scheduling for In-Field Aging Detection
Yosuke Morinaga, Tomokazu Yoneda (NAIST), Hyunbean Yi (Hanbat National Univ.), Michiko Inoue (NAIST) DC2011-85
 [more] DC2011-85
pp.55-60
DC 2011-02-14
11:50
Tokyo Kikai-Shinko-Kaikan Bldg. A Pattern Generation Method to Uniform Initial Temperature of Test Application
Emiko Kosoegawa, Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (NAIST/JST) DC2010-63
Circuit failure prediction is essential to ensure product quality and in-field reliability. The basic principle of circu... [more] DC2010-63
pp.27-32
DC 2011-02-14
13:45
Tokyo Kikai-Shinko-Kaikan Bldg. Test Pattern Generation for Highly Accurate Delay Testing
Keigo Hori (NAIST), Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (NAIST/JST) DC2010-64
We propose a new faster-than-at-speed test method to detect small delay defects. As semiconductor technology is scaling ... [more] DC2010-64
pp.33-38
ICD
(Workshop)
2010-08-16
- 2010-08-18
Overseas Ho Chi Minh City University of Technology [Invited Talk] Circuit Failure Prediction by Field Test (DART) with Delay-Shift Measurement Mechanism
Yasuo Sato, Seiji Kajihara (Kyusyu Institute of Technology), Michiko Inoue, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara (NAIST), Yukiya Miura (Tokyo Metropolitan Univ.)
The main task of test had traditionally been screening of hard defects before shipping. However, current chips are takin... [more]
DC 2010-02-15
09:25
Tokyo Kikai-Shinko-Kaikan Bldg. Test Pattern Re-Ordering for Thermal-Uniformity during Test
Makoto Nakao, Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (Nara Inst. of Sci and Tech.) DC2009-66
Power consumption during VLSI testing varies spatially and temporally, and it leads to temperature variation during tes... [more] DC2009-66
pp.7-12
DC 2010-02-15
14:35
Tokyo Kikai-Shinko-Kaikan Bldg. Seed Selection for High Quality Delay Fault Test in BIST
Akira Taketani, Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (Nara Inst. of Sci and Tech.) DC2009-74
In this paper, we target a scan BIST architecture that consists of LFSR, phase shifter and MISR, and propose a method to... [more] DC2009-74
pp.57-62
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2008-11-18
11:20
Fukuoka Kitakyushu Science and Research Park A Reconfigurable Wrapper Design for Testing Cores with Multi-Clock Domains
Takashi Yoshida, Tomokazu Yoneda, Hideo Fujiwara (Nara Institute of Science and Technology) VLD2008-82 DC2008-50
This paper presents an optimization method for designing reconfigurable test wrappers for cores with multiple clock doma... [more] VLD2008-82 DC2008-50
pp.133-138
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]
2007-11-21
14:40
Fukuoka Kitakyushu International Conference Center Thermal-Aware Test Scheduling with Cycle-Accurate Power Profiles and Test Partitioning
Thomas Edison Yu, Tomokazu Yoneda (NAIST), Krishnendu Chakrabarty (Duke Univ.), Hideo Fujiwara (NAIST) VLD2007-84 DC2007-39
Higher power densities and the non-linear spatial distribution of heat of VLSI chips put greater emphasis on chip-packag... [more] VLD2007-84 DC2007-39
pp.13-18
CAS, SIP, VLD 2007-06-22
11:30
Hokkaido Hokkaido Tokai Univ. (Sapporo) Power Constrained IP Core Wrapper Design with Partitioned Clock Domains
Thomas Edison Yu, Tomokazu Yoneda (NAIST), Danella Zhao (Unive. of Louisiana), Hideo Fujiwara (NAIST) CAS2007-25 VLD2007-41 SIP2007-55
Rapid developments in VLSI technology has made it possible to embed whole system components onto a single chip, called S... [more] CAS2007-25 VLD2007-41 SIP2007-55
pp.37-42
RECONF, CPSY, VLD, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]
2006-11-28
16:10
Fukuoka Kitakyushu International Conference Center Test Scheduling for SoCs with Built-In Self-Repairable Memory Cores
Yusuke Fukuda, Tomokazu Yoneda, Hideo Fujiwara (NAIST)
This paper presents a power-constrained test scheduling mehtod for SoCs with built-in self repairable memories which are... [more] VLD2006-61 DC2006-48
pp.59-64
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