Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
HWS, VLD |
2023-03-03 11:25 |
Okinawa |
(Primary: On-site, Secondary: Online) |
Identification of Redundant Flip-Flops Using Fault Injection for Low-Power Approximate Computing Circuits Jiaxuan Lu, Yutaka Masuda, Tohru Ishihara (Nagoya Univ.) VLD2022-104 HWS2022-75 |
(To be available after the conference date) [more] |
VLD2022-104 HWS2022-75 pp.167-172 |
OPE, LQE, OCS |
2022-05-13 16:05 |
Online |
Online |
[Special Invited Talk]
Energy efficient optoelectronic conversion and its applications to photonic integrated systems Akihiko Shinya, Kengo Nozaki, Shota Kita (NTT), Tohru Ishihara (Nagoya Univ.), Shinji Matsuo, Masaya Notomi (NTT) OCS2022-7 OPE2022-7 LQE2022-7 |
(To be available after the conference date) [more] |
OCS2022-7 OPE2022-7 LQE2022-7 pp.26-29 |
VLD, HWS [detail] |
2022-03-07 13:15 |
Online |
Online |
[Memorial Lecture]
An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers Lingxiao Hou, Yutaka Masuda, Tohru Ishihara (Nagoya Univ.) VLD2021-83 HWS2021-60 |
The logarithmic approximate multiplier proposed by Mitchell provides an efficient alternative to accurate multipliers in... [more] |
VLD2021-83 HWS2021-60 p.43 |
HWS, VLD [detail] |
2020-03-05 11:20 |
Okinawa |
Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
stochasitc fast estimation of timing error induced circuit lifetime distribution Hazuki Tomiyama, Yutaka Masuda, Tohru Ishihara (Nagoya Univ.) VLD2019-113 HWS2019-86 |
In VLSI design, a designer needs the integrated circuit to keep correct operation under area, power,
and performance co... [more] |
VLD2019-113 HWS2019-86 pp.113-118 |
HWS, VLD [detail] |
2020-03-06 17:15 |
Okinawa |
Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
Circuit Architecture Exploration for Optical Neural Network based on Integrated Nanophotonics Naoki Hattori, Yutaka Masuda, Tohru Ishihara (Nagoya Univ.), Jun Shiomi (Kyoto Univ.), Akihiko Shinya, Masaya Notomi (NTT) VLD2019-137 HWS2019-110 |
With a rapid progress of the integrated nanophotonics technology, optical neural networks
based on the integrated nano... [more] |
VLD2019-137 HWS2019-110 pp.251-256 |
HWS, VLD |
2019-02-28 14:55 |
Okinawa |
Okinawa Ken Seinen Kaikan |
[Memorial Lecture]
Methods for Reducing Power and Area of BDD-based Optical Logic Circuits Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.), Akihiko Shinya, Masaya Notomi (NTT) VLD2018-116 HWS2018-79 |
[more] |
VLD2018-116 HWS2018-79 pp.139-144 |
VLD, HWS (Joint) |
2018-03-02 11:20 |
Okinawa |
Okinawa Seinen Kaikan |
Energy Reduction of Standard-Cell Memory Exploiting Selective Activation Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.) VLD2017-124 |
On-chip memories have a large impact on energy-efficiency of LSI circuits. This paper discusses energy-efficient on-chip... [more] |
VLD2017-124 pp.211-216 |
VLD, CAS, MSS, SIP |
2016-06-17 10:10 |
Aomori |
Hirosaki Shiritsu Kanko-kan |
A Parallel Adder Circuit based on Optical Pass-gate Logic and Its Evaluation with Optoelectronic Circuit Simulator Tohru Ishihara (Kyoto Univ.), Akihiko Shinya (NTT), Koji Inoue (Kyushu Univ.), Kengo Nozaki, Masaya Notomi (NTT) CAS2016-20 VLD2016-26 SIP2016-54 MSS2016-20 |
[more] |
CAS2016-20 VLD2016-26 SIP2016-54 MSS2016-20 pp.109-114 |
VLD |
2016-03-01 17:30 |
Okinawa |
Okinawa Seinen Kaikan |
[Memorial Lecture]
A Closed-Form Stability Model for Cross-Coupled Inverters Operating in Sub-Threshold Voltage Region Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.) VLD2015-131 |
A cross-coupled inverter which is an essential element of on-chip memory subsystems plays an important role in synchrono... [more] |
VLD2015-131 p.117 |
VLD |
2015-03-03 15:50 |
Okinawa |
Okinawa Seinen Kaikan |
[Memorial Lecture]
Microarchitectural-Level Statistical Timing Models for Near-Threshold Circuit Design Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.) VLD2014-172 |
Near-threshold computing has emerged as a promising solution for drastically improving the energy efficiency of micropro... [more] |
VLD2014-172 pp.109-114 |
RECONF, CPSY, VLD, IPSJ-SLDM [detail] |
2015-01-29 17:40 |
Kanagawa |
Hiyoshi Campus, Keio University |
Analyzing the Impacts of Simultaneous Supply and Threshold Voltage Tuning on Energy Dissipation in VLSI Circuits Toshihiro Takeshita, Shinichi Nishizawa, AKM Mahfuzul Islam, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ) VLD2014-129 CPSY2014-138 RECONF2014-62 |
Simultaneous supply and threshold voltage tuning has a strong impact on the energy reduction of LSI circuits. Therefore,... [more] |
VLD2014-129 CPSY2014-138 RECONF2014-62 pp.111-116 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-28 11:20 |
Miyazaki |
NewWelCity Miyazaki |
An Interrupt Service Handler in Hardware for Ultra-Low Latency Response Naotaka Maruyama (Kernelon Silicon), Tohru Ishihara (Kyoto Univ.), Hiroaki Takada (Nagoya Univ.), Hiroto Yasuura (Kyushu Univ.) VLD2011-57 DC2011-33 |
This paper proposes an interrupt processing in hardware for achieving ultra-low interrupt latency. Several types of mach... [more] |
VLD2011-57 DC2011-33 pp.31-36 |
ICD, IE, SIP, IPSJ-SLDM [detail] |
2011-10-25 15:05 |
Miyagi |
Ichinobo(Sendai) |
Simultaneous Optimization of Cache Way Selection and Code Placement for Reducing the Memory Access Energy Consumption Junshi Takata (Kyushu Univ.), Tohru Ishihara (Kyoto Univ.), Koji Inoue (Kyushu Univ.) SIP2011-76 ICD2011-79 IE2011-75 |
The paper proposes a technique which simultaneously finds the optimal cache way allocation and code placement for given ... [more] |
SIP2011-76 ICD2011-79 IE2011-75 pp.89-94 |
DC, CPSY, IPSJ-SLDM, IPSJ-EMB |
2009-03-05 15:15 |
Niigata |
Sado Island Integrated Development Center |
A Dynamic Management Technique of a Non-Uniform Selective Way Cache for Reducing the Energy Consumption of Embedded Processors Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) CPSY2008-90 DC2008-81 |
(To be available after the conference date) [more] |
CPSY2008-90 DC2008-81 pp.13-18 |
DC, CPSY, IPSJ-SLDM, IPSJ-EMB |
2009-03-05 15:45 |
Niigata |
Sado Island Integrated Development Center |
Single-Cycle-Accessible Two-Level Cache Architecture Seiichiro Yamaguchi, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) CPSY2008-91 DC2008-82 |
A small L0-cache located between an MPU core and an L1-cache is widely used in embedded processors for reducing the ener... [more] |
CPSY2008-91 DC2008-82 pp.19-24 |
DC, CPSY, IPSJ-SLDM, IPSJ-EMB |
2009-03-05 16:15 |
Niigata |
Sado Island Integrated Development Center |
An OS-Analyzable Power Consumption Model and Its Generation Technique for Wireless Communication Devices Tohru Ishihara, Takumi Okuhira, Kenji Hisazumi (Kyushu Univ.), Takeshi Kamiyama, Kazuhisa Sekine, Masaji Katagiri (NTT Docomo) CPSY2008-92 DC2008-83 |
This paper proposes a lightweight power consumption model and its generation technique for quickly and accurately estima... [more] |
CPSY2008-92 DC2008-83 pp.25-30 |
VLD, IPSJ-SLDM |
2008-05-09 11:40 |
Hyogo |
Kobe Univ. |
Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) VLD2008-9 |
This paper describes analysis of on-chip bus power in the presence of arrival time variations of input signals. With shr... [more] |
VLD2008-9 pp.13-18 |
DC, CPSY, IPSJ-SLDM, IPSJ-EMB |
2008-03-27 08:45 |
Kagoshima |
|
An Adaptive Multi-Performance Processor and its Evaluation Seiichiro Yamaguchi, Yuichiro Oyama (Kyushu Univ.), Yuji Kunitake (Kyushu Inst. of Tech.), Tadayuki Matsumura, Yuriko Ishitobi, Masaki Yamaguchi, Donghoon Lee, Yusuke Kaneda (Kyushu Univ.), Toshimasa Funaki (Kyushu Inst. of Tech.), Masanori Muroyama, Tohru Ishihara, Toshinori Sato (Kyushu Univ.) DC2007-84 CPSY2007-80 |
This paper presents an energy efficient processor which can be used as a design alternative for the dynamic voltage scal... [more] |
DC2007-84 CPSY2007-80 pp.1-6 |
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 10:05 |
Fukuoka |
Kitakyushu International Conference Center |
A Memory Management Technique for Energy Reduction in Multi-Task Embedded Applications Seiichiro Yamaguchi, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) |
Memory systems consume a significant amount of the energy in embedded systems. Static code placement techniques using sc... [more] |
VLD2007-74 DC2007-29 pp.25-29 |
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 10:30 |
Fukuoka |
Kitakyushu International Conference Center |
An ILP Model of Code Placement Problem for Minimizing the Energy Consumption in Embedded Processors Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) |
This paper formulates a code placement problem to optimize the total energy consumption of a CPU core, on-chip memories ... [more] |
VLD2007-75 DC2007-30 pp.31-36 |