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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 16 of 16  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
NS, ASN, RCC, RCS, SR
(Joint)
2017-07-20
09:40
Hokkaido Hokkaido Univ. An IoT Monitoring Prototype System for Smart Farm Using Zigbee and Raspberry Pi Module
Hong Quy Vo, Tri Dinh Nguyen (HUSC), Thi Hong Tran (NAIST), Xuan Vinh Dang (HUSC), Yasuhiko Nakashima (NAIST) RCS2017-108
 [more] RCS2017-108
pp.91-96
RECONF, CPSY, DC, IPSJ-ARC
(Joint) [detail]
2017-05-23
14:20
Hokkaido Noboribetsu-Onsen Dai-ichi-Takimoto-Kan A Compact Low-Latency Systematic Successive Cancellation Polar Decoder for Visible Light Communication Systems
Duc Phuc Nguyen, Dinh Dung Le, Thi Hong Tran, Takashi Nakada, Yasuhiko Nakashima (NAIST) CPSY2017-2 DC2017-2
Channel polarization and Polar code are widely considered as major breakthroughs in coding theory because they have show... [more] CPSY2017-2 DC2017-2
pp.3-7
RECONF, CPSY, DC, IPSJ-ARC
(Joint) [detail]
2017-05-23
14:40
Hokkaido Noboribetsu-Onsen Dai-ichi-Takimoto-Kan A prototype of Dimmable Visible Light Communication System on FPGA
Dinh Dung Le, Duc Phuc Nguyen, Thi Hong Tran, Yasuhiko Nakashima (NAIST), Son Kiet Nguyen, Huu Thuan Huynh (HCMUS) CPSY2017-3 DC2017-3
Visible Light Communication (VLC) which provides both illumination and communication service has attracted increasing at... [more] CPSY2017-3 DC2017-3
pp.9-13
NS, RCS
(Joint)
2015-12-18
11:50
Ehime Matsuyama Community Center BER/PER Performance of 802.11ah K-best Viterbi Decoder on Fading Channel
Duc Phuc Nguyen, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) RCS2015-259
IEEE 802.11ah shows promise advantages in Internet of Things (IoT) such as extended range, power efficiency and scalable... [more] RCS2015-259
pp.93-98
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-02
11:40
Nagasaki Nagasaki Kinro Fukushi Kaikan Performance Comparison of FPGA Accelerators with Vivado HLS and PyCoRAM
Yuma Kikutani (OPUCT), Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) CPSY2015-66
High-level synthesis (HLS) technology has been an attractive and efficient method for FPGA system development. In this ... [more] CPSY2015-66
pp.27-32
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-02
12:05
Nagasaki Nagasaki Kinro Fukushi Kaikan A proposal of the light field image compression and decompression using HEVC
Takamasa Mitani, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) CPSY2015-67
A light field image is a type of images that can refocus and extend the depth of field by post processing. A light field... [more] CPSY2015-67
pp.33-38
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-02
14:35
Nagasaki Nagasaki Kinro Fukushi Kaikan Performance Evaluation of K-best Viterbi Decoder for IoT Applications
Thi Hong Tran (NAIST), Dwi Rahma Ariyani, Lina Alfaridah ZH (Andalas Univ.), Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima (NAIST) CPSY2015-70
 [more] CPSY2015-70
pp.51-56
CPSY, IPSJ-ARC 2015-10-08
10:00
Chiba Makuhari-messe [Poster Presentation] A System Employing OculusRift and Many-core Simulator for Visualizing Performance Bottlenecks
Satoshi Shimaya, Hiromasa Kato, Tomoya Kameda, Keisuke Fujimoto, Shohei Takeuchi, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) CPSY2015-46
According to the complicated internal structure of modern CPU, the cost for tuning software to get higher performance ha... [more] CPSY2015-46
pp.5-6
CPSY, IPSJ-ARC 2015-10-08
10:00
Chiba Makuhari-messe [Poster Presentation] Evaluation of a Low Power CGRA EMAX Embedded with Zynq
Shohei Takeuchi, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) CPSY2015-51
We have been proposing EMAX (Energy-Aware Multimode Accelerator
Extension) that is one of CGRAs and can employ maximum ... [more]
CPSY2015-51
pp.39-41
CPSY, DC, IPSJ-ARC
(Joint) [detail]
2015-08-04
13:30
Oita B-Con Plaza (Beppu) Implementation and Evaluation of Near Memory Processing Architecture on FPGA
Tadahiro Edamoto, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) CPSY2015-18
 [more] CPSY2015-18
pp.41-45
CPSY, DC, IPSJ-ARC
(Joint) [detail]
2015-08-04
14:00
Oita B-Con Plaza (Beppu) Evaluation of ARM-EMAX tightly coupled accelerator on Zynq
Shohei Takeuchi, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) CPSY2015-19
We focus on the data reusability of stencil computations on a previously proposed memory-network based accelerator, name... [more] CPSY2015-19
pp.47-52
DC, CPSY 2015-04-17
13:00
Tokyo   CGRA in Cache for Graph Applications
Shohei Takeuchi, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) CPSY2015-7 DC2015-7
Recently, CGRA has been suggested high-speed and lower power consumption of graph processing. Generally, CGRA is connect... [more] CPSY2015-7 DC2015-7
pp.37-41
DC, CPSY 2015-04-17
13:50
Tokyo   Near Memory Processing Architecture for High Performance Atypical Applications
Tadahiro Edamoto, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) CPSY2015-9 DC2015-9
 [more] CPSY2015-9 DC2015-9
pp.49-52
DC, CPSY 2015-04-17
17:05
Tokyo   Prototyping of GPS-based Item Finder System
Soichiro Kanagawa, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) CPSY2015-15 DC2015-15
In recent years, small high-performance equipment accumulating a large amount of information has been penetrated as poss... [more] CPSY2015-15 DC2015-15
pp.83-88
RCS 2014-06-17
10:05
Okinawa Okinawa-ken Seinenkaikan (Naha) A Design of MIMO Decoder using LLR Approximation without Maximum Value Calculation
Reina Hongyo, Thi Hong Tran, Hiroshi Ochi (Kyusyu Inst. of Tech.) RCS2014-39
In Multiple Input Multiple Output (MIMO) decoders, soft decision bits in the form of Log Likelihood Ratio (LLR) are ofte... [more] RCS2014-39
pp.43-48
RCS, SIP 2014-01-23
14:15
Fukuoka Kyushu Univ. Low Complexity Quasi MLD MIMO Decoder Using 2D Sorter
Thi Hong Tran, Reina Hongyo (Kyushu Inst. of Tech.), Yuhei Nagao (Radrix), Hiroshi Ochi (Kyushu Inst. of Tech.) SIP2013-95 RCS2013-265
This paper proposes a low complexity quasi Maximum Likelihood Detection (MLD) algorithm and hardware architecture for MI... [more] SIP2013-95 RCS2013-265
pp.59-64
 Results 1 - 16 of 16  /   
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