| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| MBE, NC (Joint) |
2016-05-21 14:15 |
Toyama | University of Toyama | Acceleration of automatic sorting system for large scale calcium imaging data Takahiro Nemoto, Teruo Tanaka, Akihiro Fujii (Kogakuin Univ.), Noriaki Ohkawa (Univ of Toyama.), Masaaki Sato, Yasunori Hayashi (RIKEN BSI.), Kaoru Inokuchi (Univ of Toyama.), Tomoki Fukai (RIKEN BSI.), Takashi Takekawa (Kogakuin Univ.)  NC2016-4 |
[more] | NC2016-4 pp.17-22 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 10:40 |
Kochi | Kochi City Culture-Plaza | Implementation of Asynchronous Bus for GALS System Takehiro Hori, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) CPM2009-135 ICD2009-64 |
Although asynchronous circuit can solve problems of power consumption, speed, noise, and clockskew, the transmission is ... [more] | CPM2009-135 ICD2009-64 pp.7-12 |
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 10:55 |
Kanagawa | A Proposal of Message Driven IP Core Interface Ryuta Sasaki, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) VLD2008-96 CPSY2008-58 RECONF2008-60 |
In a ULSI such as SoC, various IP cores with different development firms are integrated in single-chip. Therefore proble... [more] | VLD2008-96 CPSY2008-58 RECONF2008-60 pp.31-36 |
|
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-30 09:40 |
Kanagawa | Foreknown Regularity Arithmetic Processing Unit Jin Sato, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) VLD2008-111 CPSY2008-73 RECONF2008-75 |
The paper proposes a method of designing an arithmetic unit based on the regularity of the output depending on input pat... [more] | VLD2008-111 CPSY2008-73 RECONF2008-75 pp.117-122 |
|
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-30 14:45 |
Kanagawa | Implementation of Asynchronous Bus for GALS System Takehiro Hori, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) VLD2008-120 CPSY2008-82 RECONF2008-84 |
Although asynchronous circuit can solve problems of power consumption, speed, noise, and clockskew, the transmission is ... [more] | VLD2008-120 CPSY2008-82 RECONF2008-84 pp.171-176 |
|
| ICD, SIP, IE, IPSJ-SLDM | 2006-10-26 09:00 |
Miyagi | A Cryptographic Communication Technique between IP cores in ULSI Masafumi Hayakawa (Tokyo Denki Univ.), Tsugio Nakamura (Kokusai junior colleg), Hiroshi Kasahara, Narito Fuyutsume, Teruo Tanaka (Tokyo Denki Univ.) |
The paper proposes a communication method between IP cores, including the standardization on the interface between IP co... [more] | SIP2006-83 ICD2006-109 IE2006-61 pp.1-6 |
|
| ICD, SIP, IE, IPSJ-SLDM | 2006-10-26 16:35 |
Miyagi | A self-support oriented IP core design method Hiroyuki Hatakenaka (TDU), Tsugio Nakamura (Kokusai Junior College), Hiroshi Kasahara, Narito Fuyutsume, Teruo Tanaka (TDU) |
For designing an integrated circuit with the scale of System LSI or SoC, it is reasonable to reuse the circulating IP c... [more] |
SIP2006-98 ICD2006-124 IE2006-76 pp.87-92 |
|
[Return to Top Page]