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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-30 12:45 |
Kanagawa | A Low Energy ASIP Synthesis Method Based on Reducing Instruction Memory Access Yuta Kobayashi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)  VLD2008-116 CPSY2008-78 RECONF2008-80 |
In this paper, we propose an energy-efficient ASIP synthesis method based on reducing instruction memory access. Since a... [more] | VLD2008-116 CPSY2008-78 RECONF2008-80 pp.147-152 |
|
| PN, NS (Joint) |
2008-12-18 10:20 |
Hyogo | Koube Univ. | A Load-Balancing Anycast Route Selection Method for Reducing Control Packets Masayuki Yokota, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) NS2008-110 |
In anycast communications, clients can communicate with the most suitable server automatically from multiple servers whi... [more] | NS2008-110 pp.13-18 |
| PN, NS (Joint) |
2008-12-19 14:20 |
Hyogo | Koube Univ. | A fast handoff method by using NEMO for high-speed mobile terminal Atsuki Tanaka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Uni.) NS2008-123 |
[more] | NS2008-123 pp.89-94 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 15:50 |
Fukuoka | Kitakyushu Science and Research Park | Multi-Rate Compatible High Throughput Irregular LDPC Decoder Based on High-Efficiency Column Operation Unit Akiyuki Nagashima, Yuta Imai, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-66 DC2008-34 |
Low Density Parity Check (LDPC) code is expected to be an error correcting code for next generation networks since it sh... [more] | VLD2008-66 DC2008-34 pp.37-42 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 16:15 |
Fukuoka | Kitakyushu Science and Research Park | A Parallel Hardware Engine for Generating Deformed Maps Akira Arahata, Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-67 DC2008-35 |
[more] | VLD2008-67 DC2008-35 pp.43-48 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 13:00 |
Fukuoka | Kitakyushu Science and Research Park | Scan-based Attack for an AES-LSI included with other IPs Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ) VLD2008-68 DC2008-36 |
The threat of side-channel attacks of cryptography LSIs is indicated. Recently, Scan-based attacks using the scan chain... [more] |
VLD2008-68 DC2008-36 pp.49-53 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 13:25 |
Fukuoka | Kitakyushu Science and Research Park | Dynamically Variable Secure Scan Architecture against Scan-based Side Channel Attack on Cryptography LSIs Hiroshi Atobe, Ryuta Nara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-69 DC2008-37 |
Scan test is a powerful and popular test technique because it can control and observe the internal states of the circuit... [more] | VLD2008-69 DC2008-37 pp.55-59 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 13:50 |
Fukuoka | Kitakyushu Science and Research Park | A Power Masking Method of AES Circuit By Using Cross Bar Switch To Switch S-Box Circuit. Nobuyuki Kawahata, Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ) VLD2008-70 DC2008-38 |
[more] | VLD2008-70 DC2008-38 pp.61-66 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 10:30 |
Fukuoka | Kitakyushu Science and Research Park | A Two-level Cache and Scratch Pad Memory Simulation for Embedded Systems Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-76 DC2008-44 |
In an embedded system where a single application or a class of applications are repeatedly executed on a processor, its ... [more] | VLD2008-76 DC2008-44 pp.97-102 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-19 10:25 |
Fukuoka | Kitakyushu Science and Research Park | A Multiplexer Reducing Algorithm in Floorplan-Aware High-level Synthesis for Distributed-Register Architectures Tetsuya Endo, Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ) VLD2008-84 DC2008-52 |
In high level synthesis for resource shared architecture, multiplexers are inserted between registers and functional uni... [more] | VLD2008-84 DC2008-52 pp.145-150 |
| SR, RCS, USN, AN (Joint) |
2008-10-22 11:10 |
Okinawa | Okinawa industry support center | A Hybrid Routing Protocol Using Location Information for Mobile Ad Hoc Networks Shunsuke Miura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda University) AN2008-32 |
[more] | AN2008-32 pp.17-22 |
| VLD | 2008-09-29 14:45 |
Ishikawa | A DFG Mapping Algorithm for Flexible Engine/Generic ALU Array Masayuki Honma, Ryo Tamura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Makoto Satoh (Hitachi, Ltd.) VLD2008-48 |
Reconfigurable processors are processors whose contexts are dynamically reconfigured while they are working. We focus on... [more] | VLD2008-48 pp.7-12 |
|
| VLD | 2008-09-29 15:10 |
Ishikawa | FFT Design for Flexible Engine/Generic ALU Array and Its Dedicated Synthesis Algorithm Ryo Tamura, Masayuki Honma, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Makoto Satoh (Hitachi, Ltd.) VLD2008-49 |
Reconfigurable processors are those whose contexts are dynamically reconfigured while they are working. We focus on a re... [more] | VLD2008-49 pp.13-18 |
|
| VLD | 2008-09-29 16:40 |
Ishikawa | Design and Evalution of a Butterfly Circuit Using Selector Logic by Bit-Level Transformation Takeshi Namura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Motonobu Tonomura (Dai Nippon Print) VLD2008-52 |
An arithmetic circuit using selector logic has been proposed, as a high computational approach for processing. In thi... [more] |
VLD2008-52 pp.31-36 |
|
| ITS | 2008-07-28 13:00 |
Aichi | Nagoya University | A Fast Deformed Area Map Generation Algorithm Based on Road Network Partitioning Kazuya Matsumoto, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) ITS2008-12 |
As cellular phones become smaller and more powerful, a navigation system using GPS on cellular phones has expanded, and ... [more] | ITS2008-12 pp.25-30 |
| ITS | 2008-07-28 13:30 |
Aichi | Nagoya University | User's Route Preference Investigation in Indoor Environment and Its Associative Route Searching Method Takahiro Yamagishi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) ITS2008-13 |
Recently, mobile telecommunication services have been much extended and advanced with the spread of celluar phones. Howe... [more] | ITS2008-13 pp.31-36 |
| ITS | 2008-07-28 14:00 |
Aichi | Nagoya University | Recognition Rate Investigation of Various Photography Conditions for Pedestrian Positioning Using Road Traffic Signs Tomoyuki Kojima, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) ITS2008-14 |
Pedestrian navigation systems are being developed by the spread of GPS.However GPS can cause approximately 100-meter err... [more] | ITS2008-14 pp.37-42 |
| VLD, IPSJ-SLDM | 2008-05-08 16:15 |
Hyogo | Kobe Univ. | Radix-2 Butterfly Circuit Architecture Using Selector Logic Takeshi Namura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Motonobu Tonomura (Dai Nippon Print) VLD2008-5 |
An arithmetic circuit using selector logic has been proposed, as a high computational approach for processing. In thi... [more] |
VLD2008-5 pp.25-30 |
| VLD, ICD | 2008-03-05 14:40 |
Okinawa | TiRuRu | An Energy-efficent ASIP Synthesis Method Based on Reducing Bit-width of Instruction Memory Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2007-141 ICD2007-164 |
[more] | VLD2007-141 ICD2007-164 pp.25-30 |
| VLD, ICD | 2008-03-07 14:15 |
Okinawa | TiRuRu | Application-Oriented Dynamic Reconfigurable Network Processor Architecture and Its Optimization Method Motonori Ohta, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ) VLD2007-164 ICD2007-187 |
In this paper, we propose an application directional dynamic reconfigurable network processor architecture and its optim... [more] | VLD2007-164 ICD2007-187 pp.47-52 |
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