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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
DC, CPSY (Joint) |
2011-07-29 13:55 |
Kagoshima |
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An Availability Evaluation of GPU Programming Framework to Provide Embedded MPI Keigo Shima, Takefumi Miyoshi, Masaaki Kondo, Hidetsugu Irie, Hiroki Honda, Tsutomu Yoshinaga (UEC) CPSY2011-17 |
We proposed a programming framework which enables
programmers to use MPI functions within GPU kernels.
The framework a... [more] |
CPSY2011-17 pp.49-54 |
RECONF, VLD, CPSY, IPSJ-SLDM [detail] |
2011-01-18 15:30 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
A Consideration of Window Join Operator over Data Streams by using FPGA Yuta Terada, Takefumi Miyoshi (UEC), Hideyuki Kawashima (Univ. Tsukuba), Tsutomu Yoshinaga (UEC) VLD2010-111 CPSY2010-66 RECONF2010-80 |
An implementation technique of window join operator by using FPGA is studied in order to improve the performance. Window... [more] |
VLD2010-111 CPSY2010-66 RECONF2010-80 pp.181-186 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-12-01 09:30 |
Fukuoka |
Kyushu University |
A Study of Comparison between In-order and Out-of-order Processor for Many-core Processor Era Takefumi Miyoshi, Hidetsugu Irie, Yuuki Matsumura, Tsutomu Yoshinaga (UEC) CPSY2010-36 |
[more] |
CPSY2010-36 pp.25-30 |
IN, MoNA (Joint) |
2010-11-20 08:30 |
Fukuoka |
Fukuoka Institute of Technology |
ZeoBro: a Personal Life Assistance Service Platform on a PC-Cluster Yuta Tajima, Takefumi Miyoshi (UEC), Sayaka Akioka (Waseda Univ.), Tatsuya Goto, Hidetsugu Irie, Tsutomu Yoshinaga (UEC) IN2010-93 |
Most of personal life assistance services use activity data such as GPS location. Most of them require user histories be... [more] |
IN2010-93 pp.71-76 |
IPSJ-SLDM, VLD, CPSY, RECONF [detail] |
2010-01-27 11:15 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
Expansion of Hardware in a Scalable FPGA System Hironori Nakajo (Tokyo Univ. of Agr and Tech.), Takefumi Miyoshi (Tokyo Inst. of Tech.), Satoshi Funada (e-trees.Japan, Inc), Ryuichi Sakamoto (Tokyo Univ. of Agr and Tech.) VLD2009-89 CPSY2009-71 RECONF2009-74 |
Currently, in a field of high performance computing, some FPGAs are utilized to accelerate processing against some forma... [more] |
VLD2009-89 CPSY2009-71 RECONF2009-74 pp.125-130 |
CPSY |
2009-11-20 15:55 |
Kyoto |
Campus Plaza Kyoto |
A Study of Task Allocation Problem for Many-core Processor with Consideration of Network Traffic Shintaro Sano, Masahiro Sano, Shimpei Sato (Tokyo Inst. of Tech.), Takefumi Miyoshi (Tokyo Inst. of Tech./JST), Kenji Kise (Tokyo Inst. of Tech.) CPSY2009-40 |
In many-core architecture that has dozens of cores in processor, it is important to improve performance by using paralle... [more] |
CPSY2009-40 pp.31-36 |
RECONF |
2009-09-18 10:25 |
Tochigi |
Utsunomiya Univ. |
A Study of Scalable Prototyping System with Small-sized FPGAs Shimpei Watanabe, Shinya Takamaeda, Ken Kyou (Tokyo Inst. of Tech), Takefumi Miyoshi (Tokyo Inst. of Tech/JST), Kenji Kise (Tokyo Inst. of Tech) RECONF2009-31 |
In order to practically simulate many-core processor, the authors proposed ScalableCore which is a hardware simulator.
... [more] |
RECONF2009-31 pp.73-78 |
CPSY, DC (Joint) |
2009-08-04 - 2009-08-05 |
Miyagi |
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Acceleration of Monte-Carlo Go by FPGA-based Hardware Kenichi Koizumi (Univ. of Tokyo), Yasuo Ishii (NEC Corp.), Kazuki Yoshizoe (JST), Takefumi Miyoshi (Tokyo Inst. of Tech.), Yutaka Sugawara (IBM), Mary Inaba, Kei Hiraki (Univ. of Tokyo) CPSY2009-19 |
In the monte-carlo simulation of Go, it takes time to run playouts. There were attempts of accelerating
by implementing... [more] |
CPSY2009-19 pp.55-60 |
CS, SIP, CAS |
2008-03-07 13:00 |
Yamaguchi |
Yamaguchi University |
[Poster Presentation]
Code Optimization Method for Bypass Network Architechture by Evalation of DFG Toshihiro Shoji, Jin Tian, Takefumi Miyoshi, Nobuhiko Sugino (Tokyo Tech.) CAS2007-139 SIP2007-214 CS2007-104 |
For a bypass interconnected processor architecture, a heuristic code optimization method is proposed. In total power c... [more] |
CAS2007-139 SIP2007-214 CS2007-104 pp.75-78 |
CAS |
2005-01-21 14:15 |
Ishikawa |
Kanazawa Univ |
A technique to analyze bus architecture driven by data stream Takefumi Miyoshi, Nobuhiko Sugino (Tokyo Inst. of Tech.) |
[more] |
CAS2004-75 pp.19-22 |
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