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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 21 - 23 of 23 [Previous]  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2008-11-17
16:30
Fukuoka Kitakyushu Science and Research Park Evaluating the reliability of Highly Reliable Cell Circuits
Keiichi Hotta, Takashi Nakada, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima (Nara Institute of Science and Technology) VLD2008-75 DC2008-43
Recently, the shrinking process causes transistor variation and growth of error rate. Highly Reliable Cells (HRCs) have ... [more] VLD2008-75 DC2008-43
pp.91-96
DC, CPSY, IPSJ-SLDM, IPSJ-EMB 2008-03-28
13:50
Kagoshima   A Functional Unit with Small Variety of Highly Reliable Cells and Its Evaluation
Kazunori Suzuki, Takashi Nakada, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima (NAIST) DC2007-112 CPSY2007-108
Recently, the shrinking process causes growth of error rate. We have proposed new standard cells in which transistors ar... [more] DC2007-112 CPSY2007-108
pp.167-172
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]
2007-11-22
09:00
Fukuoka Kitakyushu International Conference Center Designing Soft Error Tolerant LUTs of SRAM-based FPGAs
Kohei Satoyama, Takashi Nakada, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima (NAIST) RECONF2007-43
Recently, soft error becomes a serious problem as the process shrinks. Especially, SRAMs seriously suffer from soft erro... [more] RECONF2007-43
pp.1-6
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