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Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, DC, IPSJ-ARC
(Joint) [detail]
2015-08-04
13:30
Oita B-Con Plaza (Beppu) Implementation and Evaluation of Near Memory Processing Architecture on FPGA
Tadahiro Edamoto, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) CPSY2015-18
 [more] CPSY2015-18
pp.41-45
DC, CPSY 2015-04-17
13:50
Tokyo   Near Memory Processing Architecture for High Performance Atypical Applications
Tadahiro Edamoto, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) CPSY2015-9 DC2015-9
 [more] CPSY2015-9 DC2015-9
pp.49-52
ICD, CPSY 2014-12-01
15:15
Tokyo Kikai-Shinko-Kaikan Bldg. [Poster Presentation] A Study on Intelligent Memory System for Overcomming Data Moving Bottlenecks
Tadahiro Edamoto, Shinya Takamaeda, Jun Yao, Yasuhiko Nakashima (naist) ICD2014-79 CPSY2014-91
 [more] ICD2014-79 CPSY2014-91
pp.31-33
CPSY, DC
(Joint)
2014-07-28
13:15
Niigata Toki Messe, Niigata An FPGA-based Graph Processing Accelerator with PyCoRAM
Shinya Takamaeda-Yamazaki, Tadahiro Edamoto, Jun Yao, Yasuhiko Nakashima (NAIST) CPSY2014-10
In order to improve the programmablity of FPGA-based accelerators with higher performance, we are developing PyCoRAM tha... [more] CPSY2014-10
pp.1-6
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