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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SIP, CAS, MSS, VLD | 2013-07-12 09:40 |
Kumamoto | Kumamoto Univ. | Low Power Memory Based Design Method of Constant Multipliers for Digital Filters Kosuke Kabasawa (Waseda Univ.), Tadahiko Sugibayashi (NEC), Masao Yanagisawa, Shinji Kimura (Waseda Univ.)  CAS2013-19 VLD2013-29 SIP2013-49 MSS2013-19 |
Digital Signal Processing of sounds and images are using many digital filters which conputes the summation of multiplica... [more] | CAS2013-19 VLD2013-29 SIP2013-49 MSS2013-19 pp.101-106 |
| SIP, CAS, MSS, VLD | 2013-07-12 10:00 |
Kumamoto | Kumamoto Univ. | Fine Grain Power Gating Based on Controllability Propagation and Power-off Probability Zhe Du, Jin Yu, Shinji Kimura (Waseda Univ.) CAS2013-20 VLD2013-30 SIP2013-50 MSS2013-20 |
Power gating technology has been widely used in VLSI designs for leakage power reduction by cutting off power supply to ... [more] | CAS2013-20 VLD2013-30 SIP2013-50 MSS2013-20 pp.107-112 |
| IE, SIP, ICD, VLD, IPSJ-SLDM [detail] | 2012-10-19 16:25 |
Iwate | Hotel Ruiz | Write Reduction for Non-volatile Registers Using the Max-flow Min-cut Theorem Yudai Itoi, Shinji Kimura (Waseda Univ.) VLD2012-58 SIP2012-80 ICD2012-75 IE2012-82 |
Recently, the next generation non-volatile memory/register using magnetic tunnel junction elements has been paid attent... [more] |
VLD2012-58 SIP2012-80 ICD2012-75 IE2012-82 pp.101-106 |
| IPSJ-SLDM, VLD | 2012-05-30 15:20 |
Fukuoka | Kitakyushu International Conference Center | Write Control Method Based on State Transition for Magnetic Flip-Flop Naoya Okada (Waseda Univ.), Yuichi Nakamura (NEC), Shinji Kimura (Waseda Univ.) VLD2012-3 |
In this manuscript, we propose a write control method for nonvolatile MFF(Magnetic Flip--Flop). MFF enables leakage powe... [more] | VLD2012-3 pp.13-18 |
| VLD | 2012-03-07 14:10 |
Oita | B-con Plaza | Power Efficient Design of Arithmetic Circuits Based on Embedded Memory Blocks in FPGA Xinmu Yu (Waseda Univ.), Kiyoharu Hamaguchi (Osaka Univ.), Shinji Kimura (Waseda Univ.) VLD2011-140 |
[more] | VLD2011-140 pp.121-126 |
| IPSJ-SLDM, VLD | 2011-05-19 09:55 |
Fukuoka | Kitakyushu International Conference Center | Multi-Stage Power Gating Based on Controlling Values of Logic Gates Jin Yu, Shinji Kimura (Waseda Univ.) VLD2011-7 |
Controlling value based power gating is a fine-grained power gating approach using the controlling values of logic eleme... [more] | VLD2011-7 pp.33-38 |
| VLD | 2011-03-04 14:25 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | Write Optimization for High-speed Non-volatile Memory Using Next State Function Naoya Okada (Waseda Univ.), Yuichi Nakamura (NEC), Shinji Kimura (Waseda Univ.) VLD2010-144 |
Non-volatile memory, such as MRAM and PCM, attracts attention for reducing power consumption. However, it consumes large... [more] | VLD2010-144 pp.165-170 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-12-01 15:30 |
Fukuoka | Kyushu University | Sharing of Clock Gating Modules under Multi-Stage Clock Gating Control Xin Man (Waseda Univ.), Takashi Horiyama (Saitama Univ.), Tomoo Kimura, Koji Kai (Panasonic), Shinji Kimura (Waseda Univ.) VLD2010-83 DC2010-50 |
Clock gating is an effective technique to reduce dynamic power consumption for sequential circuits. This paper shows a s... [more] | VLD2010-83 DC2010-50 pp.185-190 |
| NC, MBE (Joint) |
2010-03-10 14:35 |
Tokyo | Tamagawa University | Effects of environmental dynamics and observational uncertainty on CPG-based sensory feedback control. Shinji Kimura, Mayumi Haga (NAIST/OIST), Eiji Uchibe (OIST), Junichiro Yoshimoto, Kenji Doya (NAIST/OIST) NC2009-125 |
Central pattern generators (CPG) are a popular method for the control of rhythmic locomotion in robots. The advantage is... [more] | NC2009-125 pp.219-224 |
| IE, SIP, IPSJ-SLDM | 2008-10-07 11:30 |
Iwate | Aiina Center (Morioka) | Synthesis of partial product adders on FPGAs Taeko Matsunaga, Shinji Kimura (Waseda Univ.), Yusuke Matsunaga (Kyushu Univ.) |
[more] | SIP2008-117 IE2008-81 pp.59-64 |
| HIP | 2008-08-06 - 2008-08-07 |
Kagoshima | Kagoshima University | A Subjective Test about a Recognition of the Resolution of 3D image Masashi Tsuboi, Shinji Kimura, Tsutomu Horikoshi (NTT DoCoMo), Yasuhiro Takaki (TUAT) HIP2008-37 |
3D image using 3D display is essential to represent virtual space. In this study, we made a subjective test to evaluate ... [more] | HIP2008-37 pp.37-42 |
| VLD, CAS, SIP | 2008-06-27 09:00 |
Hokkaido | Hokkaido Univ. | Customizable Hardware/Software Evaluation Method Using Simple High-level Synthesis Chongyang Zhang (Waseda Univ.), Toshiro Isomura, Yu Suzuki (Toyota Motor Corp.), Shinji Kimura (Waseda Univ.) CAS2008-19 VLD2008-32 SIP2008-53 |
In hardware/software codesign, the functional description of an information system is optimized as a mixture of software... [more] | CAS2008-19 VLD2008-32 SIP2008-53 pp.1-6 |
| VLD, IPSJ-SLDM | 2008-05-08 14:45 |
Hyogo | Kobe Univ. | Checker Circuit Generation for System Verilog Assertions in Prototyping Verification Mengru Wang, Shinji Kimura (Waseda Univ.) VLD2008-2 |
Reduction of verification period is the crucial problem in the recent LSI designs, and prototyping/emulation technologie... [more] | VLD2008-2 pp.7-12 |
| VLD, IPSJ-SLDM | 2008-05-08 16:40 |
Hyogo | Kobe Univ. | Improvement of swtching activity aware algorithm for prefix graph synthesis Taeko Matsunaga, Shinji Kimura (Waseda Univ), Yusuke Matsunaga (Kyushu Univ) |
[more] | VLD2008-6 pp.31-36 |
| VLD, IPSJ-SLDM | 2008-05-09 13:30 |
Hyogo | Kobe Univ. | Fine-Grained Power Gating Based on the Controlling Value of Logic Gates Lei Chen (Waseda Univ.), Takashi Horiyama (Saitama Univ.), Yuichi Nakamura (NEC), Shinji Kimura (Waseda Univ.) VLD2008-10 |
Leakage power dissipation of logic gates has become an increasingly important problem. A novel fine-grained power gating... [more] | VLD2008-10 pp.19-24 |
| PRMU, IE | 2008-03-10 11:10 |
Ishikawa | A method to input a real scene for a 3D display using high-density directional images Masashi Tsuboi, Shinji Kimura, Tsutomu Horikoshi (NTT DoCoMo Inc.) IE2007-283 PRMU2007-267 |
We propose a method to input a real scene for a 3D display using high-density directional images. The 3D image is create... [more] | IE2007-283 PRMU2007-267 pp.139-144 |
|
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-22 13:50 |
Fukuoka | Kitakyushu International Conference Center | Parallel prefix adder synthesis based on Ling’s carry computation Taeko Matsunaga, Shinji Kimura (Waseda Univ.), Yusuke Matsunaga (Kyushu Univ.) |
Ling adders calculate carry propagation based on adjacent bit pairs, and can be formulated as parallel prefix adders. I... [more] |
VLD2007-97 DC2007-52 pp.49-54 |
| RECONF | 2007-09-20 16:30 |
Shiga | Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) | [Invited Talk]
Reconfigurable Architecture for Car Tuners Makoto Ozone, Katsunori Hirase, Kazuhisa Iizuka, Tatsuo Hiramatsu (SANYO), Shinji Kimura (Waseda Univ.) RECONF2007-21 |
In car tuner LSIs, the reception processing is expected to be realized by software. Therefore, a new processor suitable ... [more] | RECONF2007-21 pp.35-40 |
| SR | 2006-07-28 13:25 |
Kanagawa | YRP | Software Defined Radio with Reconfigurable Processor Based on ALU Array Architecture Makoto Ozone, Katsunori Hirase, Kazuhisa Iizuka, Hiroshi Nakajima, Tatsuo Hiramatsu (SANYO), Shinji Kimura (Waseda Univ.) SR2006-38 |
Software defined radio is expected as a next generation radio system because it will be able to provide various radio sy... [more] | SR2006-38 pp.173-178 |
| VLD, IPSJ-SLDM | 2006-05-11 14:30 |
Ehime | Ehime University | Dynamic Reconfigurable Wiring Architecture and Its Application to Hardware Mapping Shinji Kimura (Waseda Univ.) |
Reconfigurable architecture is one of key technologies to cope with bugs and the specification changes of systerm LSI. E... [more] | VLD2006-2 pp.7-12 |
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