| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, ICD | 2008-03-07 16:35 |
Okinawa | TiRuRu | New design technology of independent-Gate controlled Stacked type 3D transistor for system LSI Yu Hiroshima, Keisuke Okamoto, Keisuke Koizumi, Shigeyoshi Watanabe (Shonan Inst. of Tech.)  VLD2007-169 ICD2007-192 |
New design technology of Independent-Gate controlled Stacked type 3D transistor has feature of Independent-gate controll... [more] | VLD2007-169 ICD2007-192 pp.75-80 |
| VLD, ICD | 2008-03-07 17:00 |
Okinawa | TiRuRu | Design of High Density LSI with Three-Dimensional Transistor FinFET
-- Effect of pattern Area Reduction with CMOS Cell Library -- Keisuke Okamoto, Keisuke Koizumi, Yu Hiroshima, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-170 ICD2007-193 |
(To be available after the conference date) [more] | VLD2007-170 ICD2007-193 pp.81-86 |
| ICD, SDM | 2007-08-23 13:40 |
Hokkaido | Kitami Institute of Technology | Energy comparison between various supply voltage scheme for System LSI Satoshi Hanami, Shigeyoshi Watanabe, Manabu Kobayashi, Toshinori Takabatake (SIT) SDM2007-149 ICD2007-77 |
[more] | SDM2007-149 ICD2007-77 pp.47-50 |
| ICD, SDM | 2007-08-23 14:05 |
Hokkaido | Kitami Institute of Technology | Design of high-speed low-power dual-supply-voltage sysytem LSI taking into account of gate/sub-threshold leakage current Shigeyoshi Watanabe, Satoshi Hanami, Manabu Kobayashi, Toshinori Takabatake (SIT) SDM2007-150 ICD2007-78 |
[more] | SDM2007-150 ICD2007-78 pp.51-56 |
| ICD, SDM | 2007-08-24 13:50 |
Hokkaido | Kitami Institute of Technology | Design of High Density LSI with Three-Dimensional Transistor FinFET
-- Effect of Pattern Area Reduction with CMOS Cell Library -- Keisuke Okamoto, Keisuke Koizumi, Yu Hiroshima, Shigeyoshi Watanabe (SIT) SDM2007-163 ICD2007-91 |
New design method of system LSI with FinFET has been developed. Using planar+FinFET architecture the pattern area of CMO... [more] | SDM2007-163 ICD2007-91 pp.119-124 |
| ICD, SDM | 2007-08-24 14:15 |
Hokkaido | Kitami Institute of Technology | Ｄesign Method of system LSI with FinFET type DTMOS Yu Hiroshima, Shigeyoshi Watanabe, Keisuke Okamoto, Keisuke Koizumi (SIT) SDM2007-164 ICD2007-92 |
Planar DTMOS has a problem of increase of pattern area. Using FinFET type DTMOS excess pattern area of connect to gate a... [more] | SDM2007-164 ICD2007-92 pp.125-130 |
| SDM | 2007-03-15 14:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Impact of three-dimensional transistor on the pattern area reduction for high density ULSI Shigeyoshi Watanabe, Keisuke Okamoto, Yuu Hiroshima, Ｋｅｉｓｕｋｅ Ｋｏｉｚｕｍｉ, Makoto Oya (SIT) |
[more] | SDM2006-257 pp.15-20 |
| SDM | 2007-03-15 16:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Design method of low-power dual-supply-voltage system LSI taking into account various leakage current of MOSFET Shigeyoshi Watanabe, Satoshi Hanami, Manabu Kobayashi, Toshinori Takabatake (SIT) |
[more] | SDM2006-261 pp.39-44 |
| ICD, VLD | 2007-03-09 13:40 |
Okinawa | Mielparque Okinawa | Ｄesign Method of High Density System LSI with Three-Dimensional Transistor (FinFET)
-- Pattern Area Reduction of System LSI -- Shigeyoshi Watanabe, Keisuke Okamoto, Makoto Oya (Shonan Institute of Tech.) |
[more] | VLD2006-149 ICD2006-240 pp.51-56 |
| ICD, VLD | 2007-03-09 15:20 |
Okinawa | Mielparque Okinawa | Design method of low-power dual-supply-voltage system LSI taking into account gate/subthreshold leakage current of MOSFET Shigeyoshi Watanabe, Satoshi Hanami, Manabu Kobayashi, Toshinori Takabatake (Shonan Institute of Tech.) |
[more] | VLD2006-153 ICD2006-244 pp.75-80 |
| ICD, SIP, IE, IPSJ-SLDM | 2006-10-27 10:30 |
Miyagi | Design Method of System LSI with Three-Dimensional Transistor (FinFET)
-- Reduction of pattern Area -- Shigeyoshi Watanabe, Keisuke Okamoto, Makoto Oya (SIT) |
New design method of system LSI with FinFET has been developed. Using planar+FinFET architecture the pattern area of sys... [more] | SIP2006-105 ICD2006-131 IE2006-83 pp.25-30 |
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| ICD, SIP, IE, IPSJ-SLDM | 2006-10-27 10:50 |
Miyagi | Design method of low-power dual-supply-voltage system LSI taking into account leakage current of MOSFET Shigeyoshi Watanabe, Masaki Kanai, Akira Nagasawa, Satoshi Hanami, Manabu Kobayashi, Toshinori Takabatake (SIT) |
Reduction of power dissipation caused by dynamic current, gate leakage current, and subthreshold leakage current of dual... [more] | SIP2006-106 ICD2006-132 IE2006-84 pp.31-36 |
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| ICD, VLD | 2006-03-10 09:15 |
Okinawa | Low Power Design of System LSI in the Presence of Leakage Current of MOSFET Shigeyoshi Watanabe (Shonan Inst. of Tech.) |
Low power design of system LSI in the presence of leakage current has been described. By using parallel processing archi... [more] | VLD2005-122 ICD2005-239 pp.1-6 |
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| ICD, VLD | 2006-03-10 16:00 |
Okinawa | Impact of Three-Dimensional Transistor on the pattern area reduction for ULSI Shigeyoshi Watanabe (Shonan Inst. of Tech.) |
The impact of three-dimensional transistors, double-gate transistor, FinFET, and surrounding gate transistor (SGT) on th... [more] | VLD2005-133 ICD2005-250 pp.67-72 |
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| ICD | 2005-04-14 11:40 |
Fukuoka | A 128Mb DRAM Using a 1T Gain Cell(FBC) on SOI Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda (Toshiba), Tomoki Higashi (Toshiba Microelectronics), Mutsuo Morikado, Yoshihiro Minami, Tomoaki Shino, Hiroomi Nakajima, Kazumi Inoh, Takeshi Hamamoto, Shigeyoshi Watanabe (Toshiba) |
We report on a 128Mbit DRAM design using the capacitor-less DRAM cell or the floating body cell(FBC) on SOI. The cell of... [more] | ICD2005-5 pp.23-28 |
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