| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2009-12-14 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | [Poster Presentation]
Design Technology of stacked NAND type MRAM Shouto Tamai, Shigeyoshi Watanabe (Shonan Inst. of Tech.)  ICD2009-79 |
Design technology of stacked type MRAM using spin transistor has been described. Using 64 layer level cell structure fea... [more] | ICD2009-79 pp.19-23 |
| ICD | 2009-12-14 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | [Poster Presentation]
Design Technology of stacked NAND type 1-transistor FeRAM Koichi Sugano, Shigeyoshi Watanabe (Shonan Inst. of Tech) ICD2009-80 |
[more] | ICD2009-80 pp.25-29 |
| ICD, SDM | 2009-07-17 09:30 |
Tokyo | Tokyo Institute of Technology | Study of stacked NAND type 1-transistor FeRAM Koichi Sugano, Shigeyoshi Watanabe (Shonan Inst. of Tech.) SDM2009-108 ICD2009-24 |
[more] | SDM2009-108 ICD2009-24 pp.57-62 |
| ICD, SDM | 2009-07-17 09:55 |
Tokyo | Tokyo Institute of Technology | Study of stacked NAND type MRAM for universal memory Shouto Tamai, Shigeyoshi Watanabe (Shonan Inst. of Tech.) SDM2009-109 ICD2009-25 |
[more] | SDM2009-109 ICD2009-25 pp.63-68 |
| ICD | 2009-04-14 15:25 |
Miyagi | Daikanso (Matsushima, Miyagi) | Reading method of NAND type 1-transistor FeRAM with pulse input Koichi Sugano, Shigeyoshi Watanabe (Shonan Inst. of Tech.) ICD2009-11 |
[more] | ICD2009-11 pp.53-57 |
| ICD | 2009-04-14 15:50 |
Miyagi | Daikanso (Matsushima, Miyagi) | Study for Design Technology of stacked NAND type MRAM using spin transistor Shouto Tamai, Shigeyoshi Watanabe (Shonan Inst. of Tech.) ICD2009-12 |
[more] | ICD2009-12 pp.59-64 |
| VLD | 2009-03-13 14:50 |
Okinawa | Study of high-speed low-power system LSI for sub-threshold operation Makoto Tsurukubo, Shigeyoshi Watanabe (Shonan Inst. of Tech Graduate school) VLD2008-166 |
The effect of a basic inverter circuit that applied the DTMOS operation method to the Sub-threshold operation area by us... [more] | VLD2008-166 pp.237-241 |
|
| VLD | 2009-03-13 15:15 |
Okinawa | Reduced pattern area technology of 3D transistor for system LSI Yu Hiroshima, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2008-167 |
We designed 1 bit Full Adder with FinFET, Double-Gate transistor. FinFET, Double-Gate transistor, Stacked type transisto... [more] | VLD2008-167 pp.243-248 |
|
| VLD | 2009-03-13 15:40 |
Okinawa | Examination of Low-power system LSI architecture by scheduling algorithm Yoshikazu Sato, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2008-168 |
Reduction of power consumption of system LSI with scheduling algorithm has been described. Using CDFG the effect of powe... [more] | VLD2008-168 pp.249-254 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 15:25 |
Fukuoka | Kitakyushu Science and Research Park | Adaptive routing of the 2-D torus network based on a Turn model Kazuya Matoyama, Yasuyuki Miura, Shigeyoshi Watanabe (Shonan Institute of Technology) RECONF2008-43 |
[more] | RECONF2008-43 pp.27-32 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 15:50 |
Fukuoka | Kitakyushu Science and Research Park | Hardware Implementation Costs of Adaptive Routing in the Hierarchical Interconnection Network Masahiro Kaneko, Yasuyuki Miura, Shigeyoshi Watanabe (Shonan Institute of Technology) RECONF2008-44 |
By progress of VLSI technology, "On-Chip-Multiprocessor" which processes in parallel on a wafer has been realized, and a... [more] | RECONF2008-44 pp.33-38 |
| ICD, SDM | 2008-07-17 15:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | New design technology of Independent-Gate controlled Stacked type 3D transistor for system LSI Yu Hiroshima, Shigeyoshi Watanabe (SIT) SDM2008-137 ICD2008-47 |
[more] | SDM2008-137 ICD2008-47 pp.53-58 |
| ICD, SDM | 2008-07-18 09:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Study of high-Speed low-power system LSI for sub-threshold operation Makoto Tsurukubo, Shigeyoshi Watanabe (SIT) SDM2008-139 ICD2008-49 |
[more] | SDM2008-139 ICD2008-49 pp.65-70 |
| ICD, SDM | 2008-07-18 09:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Examination of Low-power system LSI architecture by Real time scheduling Yoshikazu Sato, Shigeyoshi Watanabe (SIT) SDM2008-140 ICD2008-50 |
Reduction of power consumption of system LSI with fixed priority scheduling has been described. Scheme of power supply f... [more] | SDM2008-140 ICD2008-50 pp.71-76 |
| ICD, SDM | 2008-07-18 14:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Realistic future trend of non-voltile semiconductor memory and feasibility study of ultra-low-cost high-speed universal non-volatile memory
-- feasibility study of BiCS type FeRAM and MRAM -- Shigeyoshi Watanabe, Koichi Sugano, Shouto Tamai (Shonan Institute of Tech.) SDM2008-145 ICD2008-55 |
[more] | SDM2008-145 ICD2008-55 pp.97-102 |
| ICD | 2008-04-18 16:10 |
Tokyo | Realistic future trend of non-volatile semiconductor memory and feasibility study of ultra-low-cost high-speed universal non-volatile memory
-- feasibility study of BiCS type FeRAM -- Shigeyoshi Watanabe (Shonan Institute of Tech.) ICD2008-16 |
[more] | ICD2008-16 pp.83-88 |
|
| SDM | 2008-03-14 15:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Realistic future trend of advanced non-volatile memory and feasibility study of ultra-low-cost high-speed universal non-volatile memory Shigeyoshi Watanabe (SIT) SDM2007-278 |
[more] | SDM2007-278 pp.27-32 |
| SDM | 2008-03-14 16:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | New design technology of independent-gate controlled Double-Gate transistor for LSI Yu Hiroshima, Keisuke Okamoto, Shigeyoshi Watanabe (Shonan Inst. of Tech.) SDM2007-279 |
[more] | SDM2007-279 pp.33-38 |
| VLD, ICD | 2008-03-06 16:35 |
Okinawa | TiRuRu | Comparison of Power consumption between dynamic voltage scheme and multi-supply voltage scheme for system LSI Satoshi Hanami, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-155 ICD2007-178 |
Reduction of power dissipation caused by dynamic current, gate leakage current, and subthreshold leakage current of mult... [more] | VLD2007-155 ICD2007-178 pp.67-72 |
| VLD, ICD | 2008-03-07 16:10 |
Okinawa | TiRuRu | New technology of independent-gate controlled Double-Gate transistor for system LSI Yu Hiroshima, Keisuke Okamoto, Keisuke Koizumi, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-168 ICD2007-191 |
New design technology of independent-gate controlled Double-Gate transistor realized high density design more than FinFE... [more] | VLD2007-168 ICD2007-191 pp.69-74 |
[Return to Top Page]