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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2012-01-26 16:40 |
Kanagawa | Hiyoshi Campus, Keio University | Study of pattern area and reconfigurable logic circuit with DG/CNT transistor Takamichi Hayashi, Shigeyoshi Watanabe (SIT)  VLD2011-119 CPSY2011-82 RECONF2011-78 |
Pattern area for 2~6 input reconfigurable logic circuit with double-gate (DG), Carbon-Nano-Tube (CNT), double-gate and C... [more] | VLD2011-119 CPSY2011-82 RECONF2011-78 pp.163-168 |
| ICD, IPSJ-ARC | 2012-01-20 11:10 |
Tokyo | Design Technology of stacked Type Chain PRAM Sho Kato, Shigeyoshi Watanabe (SIT) ICD2011-140 |
[more] | ICD2011-140 pp.61-66 |
|
| SDM | 2011-11-11 14:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Design Technology of stacked Type Chain PRAM Sho Kato, Shigeyoshi Watanabe (SIT) SDM2011-127 |
Stacked type chain PRAM which enables to realize lower cost than NAND flash memory has been newly proposed. Cell structu... [more] | SDM2011-127 pp.69-74 |
| SDM | 2011-11-11 16:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Study of pattern area reduction for standard cell with planar and SGT transistor Takahiro Kodama, Shigeyoshi Watanabe (SIT) SDM2011-131 |
[more] | SDM2011-131 pp.93-98 |
| SDM, ICD | 2011-08-25 09:00 |
Toyama | Toyama kenminkaikan | Study of pattern area reduction with 3 dimensional transistor for logic circuit Takahiro Kodama, Shigeyoshi Watanabe (SIT), Yu Hiroshima (Oi Electric) SDM2011-71 ICD2011-39 |
[more] | SDM2011-71 ICD2011-39 pp.1-6 |
| SDM, ICD | 2011-08-25 09:25 |
Toyama | Toyama kenminkaikan | Study of pattern area reduction for standard cell with planar and SGT transistor Takahiro Kodama, Shigeyoshi Watanabe (SIT) SDM2011-72 ICD2011-40 |
[more] | SDM2011-72 ICD2011-40 pp.7-12 |
| SDM, ICD | 2011-08-25 09:50 |
Toyama | Toyama kenminkaikan | Study of pattern area for reconfigurable logic circuit with DG/CNT transistor Takamichi Hayashi, Shigeyoshi Watanabe (SIT) SDM2011-73 ICD2011-41 |
Pattern area for 2~6 input reconfigurable logic circuit with double-gate (DG), Carbon-Nano-Tube (CNT), double-gate and C... [more] | SDM2011-73 ICD2011-41 pp.13-16 |
| SDM | 2011-07-04 17:00 |
Aichi | VBL, Nagoya Univ. | Design of stacked NOR type PRAM with phase change channel transistor Sho Kato, Shigeyoshi Watanabe (Shonan Institute of Technology) SDM2011-69 |
In this paper stacked NOR type PRAM with phase change channel transistor has been newly proposed. Fast access time compe... [more] | SDM2011-69 pp.109-113 |
| SDM | 2011-07-04 17:20 |
Aichi | VBL, Nagoya Univ. | Design method of system LSI with low power device Ryosuke Suzuki, Shigeyoshi Watanabe (Shonan Inst. Tech.) SDM2011-70 |
Design method of system LSI such as inverter, NAND, and full adder with low power tunnel transistor has been described. ... [more] | SDM2011-70 pp.115-119 |
| IPSJ-SLDM, SIP, IE, ICD [detail] | 2010-10-05 13:20 |
Chiba | Makuhari Messe, International Conference Hall | Study of stacked NOR type MRAM using spin transistor Shouto Tamai, Shigeyoshi Watanabe (sit) SIP2010-55 ICD2010-69 IE2010-73 |
In this paper stacked NOR type MRAM with vertical spin transistor has been newly proposed. Word line scheme surrounded b... [more] | SIP2010-55 ICD2010-69 IE2010-73 pp.37-42 |
| IPSJ-SLDM, SIP, IE, ICD [detail] | 2010-10-05 13:40 |
Chiba | Makuhari Messe, International Conference Hall | Pattern Layout Methods of System LSI with SGT Takahiro Kodama, Shigeyoshi Watanabe (SIT) SIP2010-56 ICD2010-70 IE2010-74 |
The pattern area reduction of inverter, NAND, and full adder with SGT and stacked SGT has been ‘newly’ estimated. Wring ... [more] | SIP2010-56 ICD2010-70 IE2010-74 pp.43-48 |
| ICD, SDM | 2010-08-27 11:40 |
Hokkaido | Sapporo Center for Gender Equality | Study of stacked MRAM for universal memory Shouto Tamai, Shigeyoshi Watanabe (Shonan Inst. of Tech.) SDM2010-142 ICD2010-57 |
In this paper stacked NOR type MRAM with vertical spin transistor has been newly proposed. Word line scheme surrounded b... [more] | SDM2010-142 ICD2010-57 pp.99-104 |
| ICD, SDM | 2010-08-27 12:05 |
Hokkaido | Sapporo Center for Gender Equality | Study of stacked FeRAM using ITO channel Koichi Sugano, Shigeyoshi Watanabe (Shonan Inst. of Tech) SDM2010-143 ICD2010-58 |
[more] | SDM2010-143 ICD2010-58 pp.105-110 |
| ICD, SDM | 2010-08-27 15:10 |
Hokkaido | Sapporo Center for Gender Equality | Circuit design of reconfigurable logic based on MOS double gate/Carbon Nano Tube transistor Takamichi Hayashi, Shigeyoshi Watanabe (Shonan Inst. of Tech.) SDM2010-148 ICD2010-63 |
Reconfigurable logic for more than 3input based on MOS double gate / Carbon Nano Tube transistor has been newly proposed... [more] | SDM2010-148 ICD2010-63 pp.131-136 |
| ICD, SDM | 2010-08-27 15:35 |
Hokkaido | Sapporo Center for Gender Equality | Pattern Layout Methods of System LSI with SGT Takahiro Kodama, Shigeyoshi Watanabe (Shonan Inst. of Tech.) SDM2010-149 ICD2010-64 |
The pattern area reduction of inverter, NAND, and full adder with SGT and stacked SGT has been ‘newly’ estimated. Wring ... [more] | SDM2010-149 ICD2010-64 pp.137-142 |
| SDM | 2010-06-22 15:35 |
Tokyo | An401・402 Inst. Indus. Sci., The Univ. of Tokyo | Study of pattern area reduction for System LSI with SGT and stacked SGT Takahiro Kodama, Shigeyoshi Watanabe (Shonan Inst. of Tech.) SDM2010-45 |
[more] | SDM2010-45 pp.67-72 |
| SDM | 2010-06-22 15:55 |
Tokyo | An401・402 Inst. Indus. Sci., The Univ. of Tokyo | Study of stacked NOR type MRAM for universal memory Shouto Tamai, Shigeyoshi Watanabe (Shonan Inst. of Tech.) SDM2010-46 |
[more] | SDM2010-46 pp.73-78 |
| ICD | 2010-04-23 10:20 |
Kanagawa | Shonan Institute of Tech. | Design Technology of stacked NAND FeRAM Koichi Sugano, Shigeyoshi Watanabe (Shonan Inst. of Tech.) ICD2010-13 |
[more] | ICD2010-13 pp.69-74 |
| ICD | 2010-04-23 10:45 |
Kanagawa | Shonan Institute of Tech. | Study of stacked NOR type MRAM Shouto Tamai, Shigeyoshi Watanabe (sit) ICD2010-14 |
[more] | ICD2010-14 pp.75-80 |
| ICD | 2009-12-14 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | [Poster Presentation]
Reducing pattern area technology of 3D transistor for system LSI Yu Hiroshima, Shigeyoshi Watanabe (Shonan Inst. of Tech.) ICD2009-78 |
We designed 1 bit Full Adder with FinFET, Double-Gate transistor. FinFET, Double-Gate transistor, Stacked type transisto... [more] | ICD2009-78 pp.13-18 |
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