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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IN | 2010-12-17 13:30 |
Hiroshima | Hiroshima City Univ. | Issues on the testbed for cloud computing technologies Shinsuke Miwa, Toshiyuki Miyachi (NICT), Takeshi Nakagawa (FJH), Hiroshi Nakai, Satoshi Ohta (NICT)  IN2010-112 |
Structure of the system on cloud computing environments will grown to be more complicated than on a legacy ICT system, w... [more] | IN2010-112 pp.87-92 |
| ICD (Workshop) |
2010-08-16 - 2010-08-18 |
Overseas | Ho Chi Minh City University of Technology | [Invited Talk]
Circuit Failure Prediction by Field Test (DART) with Delay-Shift Measurement Mechanism Yasuo Sato, Seiji Kajihara (Kyusyu Institute of Technology), Michiko Inoue, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara (NAIST), Yukiya Miura (Tokyo Metropolitan Univ.) |
The main task of test had traditionally been screening of hard defects before shipping. However, current chips are takin... [more] | |
| DC | 2010-06-25 13:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Full Scan Design Method for Asynchronous Sequential Circuits Based on C-element Scan Paths Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (NAIST) DC2010-8 |
Using asynchronous VLSI designs resolve synchronous circuit design difficulties, e.g.\ the clock skew, higher throughput... [more] | DC2010-8 pp.1-6 |
| IA, SITE, IPSJ-IOT [detail] | 2010-03-02 13:45 |
Miyagi | Stability Verification of Miniture Internet Using Live Traffic Satoshi Ohta, Toshiyuki Miyachi, Shinsuke Miwa (NICT), Hiroaki Hazeyama, Masatoshi Enomoto (NAIST), Yoichi Shinoda (JAIST) SITE2009-66 IA2009-118 |
We have been developing a method to construct a realistic environment that simulates the Internet on a testbed. To ... [more] |
SITE2009-66 IA2009-118 pp.259-264 |
|
| IA | 2009-09-25 14:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Reconstructing StarBED Physical Configuration for Providing Security and Usability Satoshi Ohta, Toshiyuki Miyachi (NICT), Takeshi Nakagawa (FJH), Satoshi Uda (JAIST), Shinsuke Miwa (NICT), Ken-ichi Chinen, Yoichi Shinoda (JAIST) IA2009-37 |
Experiments on large-scale network testbed based on actual nodes become important for evaluating binary code of software... [more] | IA2009-37 pp.23-27 |
| DC | 2009-02-16 15:45 |
Tokyo | Resource Binding to Minimize the Number of RTL Paths Yuichi Uemoto, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (Nara Inst. of Scie and Tech.) DC2008-77 |
Though path delay testing is promising to detect small delay in a VLSI circuit, it has a practical problem that the numb... [more] | DC2008-77 pp.55-60 |
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| VLD, CAS, SIP | 2008-06-27 09:40 |
Hokkaido | Hokkaido Univ. | An Approach to RTL-GL Path Mapping Based on Functional Equivalence Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara (NAIST) CAS2008-21 VLD2008-34 SIP2008-55 |
Information on false paths in a circuit is useful for design and test. The use of this information may contribute not o... [more] | CAS2008-21 VLD2008-34 SIP2008-55 pp.13-18 |
| DC | 2008-02-08 14:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | RTL False Path Identification Using High Level Synthesis Information Naotsugu Ikeda, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (NAIST) DC2007-77 |
This paper proposes a method of RTL false path identification using high level synthesis information. By using the false... [more] | DC2007-77 pp.63-68 |
| EA, SIP | 2007-05-25 10:30 |
Osaka | Osaka Univ. | A study on acoustic echo cancellation using sub-adaptive filter Satoshi Ohta, Yoshinobu Kajikawa, Yasuo Nomura (Kansai Univ.) EA2007-19 SIP2007-23 |
[more] | EA2007-19 SIP2007-23 pp.9-14 |
| CAS | 2007-01-30 12:20 |
Ehime | Ehime Univ. | A Test Generation Framework using Checker Circuits and its Application to Path Delay Test Generation Tsuyoshi Iwagaki (JAIST), Satoshi Ohtake (NAIST), Mineo Kaneko (JAIST), Hideo Fujiwara (NAIST) |
[more] | CAS2006-76 pp.37-42 |
| ICD, IPSJ-ARC | 2006-06-08 15:30 |
Kanagawa | Design for Testability of Software-Based Self-Test for Processors Masato Nakazato, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (NAIST) |
In this paper, we propose a design for testability method for test programs of software-based self-test using test progr... [more] | ICD2006-48 pp.49-54 |
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| EA, SIP | 2006-05-26 09:40 |
Hyogo | EGRET Himeji | Improvement Method of Acoustic Echo Canceller with Sub Adaptive Filter Satoshi Ohta, Yoshinobu Kajikawa, Yasuo Nomura (Kansai Univ.) |
In the acoustic echo canceller, it is generally desirable to make adjustment of an adaptive filter(ADF) small, as the es... [more] | EA2006-16 SIP2006-20 pp.1-6 |
| VLD, ICD, DC, IPSJ-SLDM | 2005-12-01 09:30 |
Fukuoka | Kitakyushu International Conference Center | Delay Testing for Application-Specific Interconnects of FPGAs based on Inphase Structure Kosuke Yabuki, Satoshi Ohtake, Hideo Fujiwara (NAIST) |
This paper presents a method of path delay fault testing for application-specific interconnects in field-programmable ga... [more] | VLD2005-61 ICD2005-156 DC2005-38 pp.1-6 |
| VLD, ICD, DC, IPSJ-SLDM | 2005-12-02 09:55 |
Fukuoka | Kitakyushu International Conference Center | A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits Tsuyoshi Iwagaki (JAIST), Satoshi Ohtake, Hideo Fujiwara (NAIST) |
This paper presents a broadside test generation method for transition faults in partial scan circuits. In order to gene... [more] |
VLD2005-77 ICD2005-172 DC2005-54 pp.7-12 |
| IN | 2005-02-17 13:50 |
Aichi | Aichi University of Technology | An Evaluation of Sensor Network Systems with Mobile Agents Using Multi Agent Simulator Satoshi Ohtake, Takashi Okuda, Tetsuo Ideguchi (Aichi Prefectural Univ.), Takahiro Horiba (Aichi Inst) |
In a ubiquitous network society, networking environment will become large scale and more complex structure. In the netwo... [more] | IN2004-176 pp.13-18 |
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