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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 61 - 80 of 206 [Previous]  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, IPSJ-SLDM 2016-05-11
14:30		 Fukuoka Kitakyushu International Conference Center A High-Level Synthesis Algorithm using Critical Path Optimization Based Operation Chainings for RDR Architectures
Kotaro Terada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2016-4		 In deep-submicron era, interconnection delays are not negligible even in high-level synthesis. RDR (Regular Distributed ... [more] VLD2016-4
pp.41-46
VLD 2016-03-01
09:50		 Okinawa Okinawa Seinen Kaikan Evaluation of Rotator-based Multiplexer Network with Control Circuits for Field-data Extractors
Koki Ito, Kazushi Kawamura (Waseda Univ.), Yutaka Tamiya (Fujitsu Lab.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-120		 In this paper, we evaluate the number of gates required for rotator-based MUX network including control circuits. Experi... [more] VLD2015-120
pp.55-60
VLD 2016-03-01
11:20		 Okinawa Okinawa Seinen Kaikan Timing-error-tolerant AES Cipher
Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-123		 With the technologies advance, the importance of crypto circuits is increasing as well. AES cipher is well known as theo... [more] VLD2015-123
pp.73-78
VLD 2016-03-01
11:45		 Okinawa Okinawa Seinen Kaikan In-situ Hardware-Trojan Authentication for Invalidating Malicious Functions
Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-124		  [more] VLD2015-124
pp.79-84
VLD 2016-03-01
15:10		 Okinawa Okinawa Seinen Kaikan FPGA Implementation of a Distributed-register Architecture Circuit Using floorplan-aware High-level Synthesis
Koichi Fujiwara, Kawamura Kazushi, Keita Igarashi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-127		 Recently, high-level synthesis techniques for FPGA designs (FPGA-HLS) are much focused on such as in image processing an... [more] VLD2015-127
pp.93-98
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-21
13:25		 Kanagawa Hiyoshi Campus, Keio University A floorplan-driven high-level synthesis algorithm resilient to dynamic delay variations
Koki Igawa, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-105 CPSY2015-137 RECONF2015-87		 Recently, we have proposed a multi-scenario high-level synthesis algorithm targeting static process variations. The algo... [more] VLD2015-105 CPSY2015-137 RECONF2015-87
pp.209-214
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-21
14:15		 Kanagawa Hiyoshi Campus, Keio University Write-Reduction using Encoding data on MLC for Non-Volatile Memories
Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-107 CPSY2015-139 RECONF2015-89		 There is a movement to use the non-volatile memory to the important main memory in von Neumann computer.
Non-volatile m... [more]		 VLD2015-107 CPSY2015-139 RECONF2015-89
pp.221-225
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2015-12-02
17:35		 Nagasaki Nagasaki Kinro Fukushi Kaikan A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay and Clock Skew in FPGA Designs
Koichi Fujiwara, kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-54 DC2015-50		 With recent process scaling in FPGAs, interconnection delays and clock skews have a large impact on the latency of a cir... [more] VLD2015-54 DC2015-50
pp.99-104
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2015-12-02
15:55		 Nagasaki Nagasaki Kinro Fukushi Kaikan A low-power soft error tolerant latch scheme on 15nm process
Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ.) VLD2015-56 DC2015-52		 In recent technology scaling, reliability of integrated circuits due to a soft error is becoming more critical than ever... [more] VLD2015-56 DC2015-52
pp.123-127
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2015-12-03
09:45		 Nagasaki Nagasaki Kinro Fukushi Kaikan Hardware Trojan Identification based on Netlist Features using SVM
Kento Hasegawa, Oya Masaru, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-58 DC2015-54		 Recently, third-party IC vendors are very often used due to
globalization and cost-reduction in the IC market but malic... [more]		 VLD2015-58 DC2015-54
pp.135-140
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2015-12-03
10:10		 Nagasaki Nagasaki Kinro Fukushi Kaikan A Quantitative Criterion of Gate-Level Netlist Vulnerability
Masaru Oya, Youhua Shi (Waseda Univ.), Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo (NEC), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-59 DC2015-55		 Recently, digital ICs are designed by outside vendors to reduce costs in semiconductor industry.
This circumstance intr... [more]		 VLD2015-59 DC2015-55
pp.141-146
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2015-12-03
12:05		 Nagasaki Nagasaki Kinro Fukushi Kaikan A Data-dependent Approximation-circuit Design using Timing-error Prediction Scheme and its Evaluations on FPGA
Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-66 DC2015-62		 The propagation delay and the transition probability along each path inside an LSI widely vary depending on input data, ... [more] VLD2015-66 DC2015-62
pp.183-188
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2015-12-03
14:35		 Nagasaki Nagasaki Kinro Fukushi Kaikan Hash-table and Balanced-tree based FIB Architecture for CCN Routers Reducing Memory Accesses
Kenta Shimazaki (Waseda Univ.), Takashi Aoki, Takahiro Hatano, Takuya Otsuka, Akihiko Miyazaki (NTT), Toshitaka Tsuda, Yong-Jin Park, Nozomu Togawa (Waseda Univ.) VLD2015-75 DC2015-71		 In conventional IP network, an IP router just forwards a packet to
another router.
Recently, Content Centric Networki... [more]		 VLD2015-75 DC2015-71
pp.243-248
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2015-12-03
15:00		 Nagasaki Nagasaki Kinro Fukushi Kaikan A Circuit Area-Aware Bit-Write Reduction Code Generation for Non-Volatile Memories
Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-76 DC2015-72		 Recently, due to low leakage power and non-volatility, the non-volatile memory technology has advanced remarkably.
Howe... [more]		 VLD2015-76 DC2015-72
pp.249-253
VLD, IPSJ-SLDM 2015-05-14
15:25		 Fukuoka Kitakyushu International Conference Center AES Encryption Circuit against Clock Glitch based Fault Analysis
Daisuke Hirano, Youhua Shi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ) VLD2015-7		 Recently, fault analysis has attracted a lot of attentions as a new kind of side channel attack methods,in which malicio... [more] VLD2015-7
pp.51-55
VLD 2015-03-03
09:15		 Okinawa Okinawa Seinen Kaikan A low-power soft error tolerant latch scheme
Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ.) VLD2014-162		 In recent technology scaling, reduction of reliability by soft-error and increase power has appeared as an inevitable pr... [more] VLD2014-162
pp.55-60
VLD 2015-03-03
16:15		 Okinawa Okinawa Seinen Kaikan [Memorial Lecture] A Bit-Write Reduction Method based on Error-Correcting Codes for Non-Volatile Memories
Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-173		 Non-volatile memory is superior to SRAM in terms of its high density and low leakage power
but it consumes larger writ... [more]		 VLD2014-173
p.115
VLD 2015-03-04
13:25		 Okinawa Okinawa Seinen Kaikan A Score-Based Hardware-Trojan Identification Method for Gate-Level Netlists
Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-182		 Recently, digital ICs are designed by outside vendors to reduce costs
in semiconductor industry. This circumstance intr... [more]		 VLD2014-182
pp.165-170
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
10:50		 Kanagawa Hiyoshi Campus, Keio University A Hardware Trojan Detection Method based on Trojan net features
Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-137 CPSY2014-146 RECONF2014-70		 Recently, digital ICs are designed by outside vendors to reduce costs
in semiconductor industry. This circumstance intr... [more]		 VLD2014-137 CPSY2014-146 RECONF2014-70
pp.157-162
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2014-11-26
09:15		 Oita B-ConPlaza Design of Flip-Flop with Timing Error Tolerance
Taito Suzuki, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (SIT), Masao Yanagisawa (Waseda Univ.) VLD2014-79 DC2014-33		 Under the influence of the miniaturization of the integrated circuit, the variation of the operation condition of the ci... [more] VLD2014-79 DC2014-33
pp.45-50
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