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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 53  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, RECONF, ICD, IPSJ-SLDM
(Joint) [detail]
2020-11-18
14:50
Online Online Evaluation of operating performance of ECDSA hardware module II
Yuya Takahashi, Takuya Matsumaru, Kazuki Monta (Kobe Univ.), Toshihiro Sato, Takaaki Okidono (ECSEC Lab), Takuji Miki, Noriyuki Miura, Makoto Nagata (Kobe Univ.)
 [more]
ICD, SDM, ITE-IST [detail] 2020-08-06
13:50
Online Online Over-the-top Si Interposer Embedding Backside Buried Metal to Reduce Power Supply Impedance
Takuji Miki, Makoto Nagata, Akihiro Tsukioka (Kobe Univ.), Noriyuki Miura (Osaka Univ.), Takaaki Okidono (ECSEC), Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi (AIST) SDM2020-5 ICD2020-5
A 2.5D structure with a Si interposer stacked on a CMOS chip is developed to reduce power supply impedance. A backside b... [more] SDM2020-5 ICD2020-5
pp.19-24
HWS, VLD [detail] 2020-03-07
13:00
Okinawa Okinawa Ken Seinen Kaikan An Inductive Impulse Self-Destructor in Sense-and-React Countermeasure Against Physical Attacks
Sho Tada, Kohei Matsuda, Makoto Nagata (Kobe Univ.), Kazuo Sakiyama (UEC), Noriyuki Miura (Kobe Univ.) VLD2019-141 HWS2019-114
 [more] VLD2019-141 HWS2019-114
pp.275-277
HWS, VLD [detail] 2020-03-07
13:25
Okinawa Okinawa Ken Seinen Kaikan Side-channel leakage evaluation of cryptographic module by IC chip level power supply noise simulation
Kazuki Yasuda, Kazuki Monta, Akihiro Tsukioka, Noriyuki Miura, Makoto Nagata (Kobe Univ), Karthik Srinivasan, Shan Wan, Lagn Lin, Ying-Shiun Li, Norman Chang (ANSYS) VLD2019-142 HWS2019-115
In this research, we focused on power supply noise as one of the observed side channel information leakage in cryptograp... [more] VLD2019-142 HWS2019-115
pp.279-282
HWS, VLD [detail] 2020-03-07
13:50
Okinawa Okinawa Ken Seinen Kaikan Light-Weight Design Methodology of Bulk Current Sensor Against Laser Fault Injection Attack on Cryptographic Processor
Yuki Yamashita, Kohei Matsuda, Makoto Nagata, Noriyuki Miura (Kobe Univ.) VLD2019-143 HWS2019-116
 [more] VLD2019-143 HWS2019-116
pp.283-284
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2019-11-15
10:05
Ehime Ehime Prefecture Gender Equality Center Evaluation of operating performance of ECDSA hardware module
Yuya Takahashi, Monta kazuki (Kobe Univ.), Toshihiro Sato, Takaaki Okidono (ECSEC Lab), Takuji Miki, Noriyuki Miura, Makoto Nagata (Kobe Univ.) ICD2019-35 IE2019-41
There are limits to how much IoT power and encryption speed can be improved at the software level. Therefore, it is nece... [more] ICD2019-35 IE2019-41
pp.37-40
HWS, ICD [detail] 2019-11-01
14:55
Osaka DNP Namba SS Bld. Countermeasures for power noise and side-channel leakage in crypto modules (Ⅱ)
Kazuki Monta, Akihiro Tsukioka, Daichi Nakagawa, Kazuki Yasuoka, Noriyuki Miura, Makoto Nagata (Kobe Univ.), Karthik Srinivasan, Shan Wan, Lang Lin, Ying-Siun Li, Norman Chang (ANSYS) HWS2019-61 ICD2019-22
 [more] HWS2019-61 ICD2019-22
pp.25-28
EMCJ, MW, EST, IEE-EMC [detail] 2019-10-25
15:55
Miyagi Tohoku Gakuin University(Conf. Room 2, Eng. Bldg. 1) Noise Suppression with Magnetic Composite Sheets in IC chip packaging and Improvements of Wireless Communication Performance
Koh Watanabe, Kosuke Jike, Satoshi Tanaka, Noriyuki Miura, Makoto Nagata (Kobe Univ.), Akihiro Takahashi, Yasunori Miyazawa, Masahiro Yamaguchi (Tohoku Univ.) EMCJ2019-67 MW2019-96 EST2019-75
Magnetic composite sheets of ferrite powders were newly packaged between an IC chip and an interposer substrate as a new... [more] EMCJ2019-67 MW2019-96 EST2019-75
pp.175-178
SDM, ICD, ITE-IST [detail] 2019-08-09
12:00
Hokkaido Hokkaido Univ., Graduate School /Faculty of Information Science and Evaluation of IC-Chip Noise Reduction using Magnetic Materials
Kosuke Jike, Koh Watanabe, Satoshi Tanaka, Noriyuki Miura, Makoto Nagata (Kobe Univ), Akihiro Takahashi, Yasunori Miyazawa, Masahiro Yamaguchi (Tohoku Univ) SDM2019-49 ICD2019-14
Suppression of noise emitted from digital integrated circuit (IC) chip is expected by using magnetic materials. The freq... [more] SDM2019-49 ICD2019-14
pp.79-83
ISEC, SITE, ICSS, EMM, HWS, BioX, IPSJ-CSEC, IPSJ-SPT [detail] 2019-07-23
13:35
Kochi Kochi University of Technology Side-channel leakage evaluation of cryptographic module by IC chip level consumption simulation
Kazuki Yasuda, Kazuki Monta, Akihiro Tsukioka, Noriyuki Miura, Makoto Nagata (Kobe Univ.) ISEC2019-27 SITE2019-21 BioX2019-19 HWS2019-22 ICSS2019-25 EMM2019-30
With the development of the information society, side-channel information leakage due to power supply noise in a cryptog... [more] ISEC2019-27 SITE2019-21 BioX2019-19 HWS2019-22 ICSS2019-25 EMM2019-30
pp.139-143
ISEC, SITE, ICSS, EMM, HWS, BioX, IPSJ-CSEC, IPSJ-SPT [detail] 2019-07-24
14:10
Kochi Kochi University of Technology Design of Highly Efficient AES Hardware Architectures Based on Multiplicative-Offset
Rei Ueno (Tohoku Univ.), Sumio Morioka (IST), Noriyuki Miura, Kohei Matsuda, Makoto Nagata (Kobe Univ.), Shivam Bhasin (NTU), Yves Mathieu, Tarik Graba, Jean-Luc Danger (TPT), Naofumi Homma (Tohoku Univ.) ISEC2019-58 SITE2019-52 BioX2019-50 HWS2019-53 ICSS2019-56 EMM2019-61
This paper presents high throughput/gate hardware architectures. In order to achieve a high area-time efficiency, the pr... [more] ISEC2019-58 SITE2019-52 BioX2019-50 HWS2019-53 ICSS2019-56 EMM2019-61
pp.375-382
ISEC, SITE, ICSS, EMM, HWS, BioX, IPSJ-CSEC, IPSJ-SPT [detail] 2019-07-24
15:00
Kochi Kochi University of Technology Potential Method to Extract Uniqueness from Non-Ideality of Sensor Device
Thibaut Constant, Makoto Nagata, Noriyuki Miura (Kobe Univ.) ISEC2019-60 SITE2019-54 BioX2019-52 HWS2019-55 ICSS2019-58 EMM2019-63
 [more] ISEC2019-60 SITE2019-54 BioX2019-52 HWS2019-55 ICSS2019-58 EMM2019-63
pp.389-390
ISEC 2019-05-17
11:00
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology (from DSD 2018)
Jean-Luc Danger (Telecom ParisTech), Risa Yashiro (UEC), Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet (Telecom ParisTech), Kazuo Sakiyama (UEC), Noriyuki Miura, Makoto Nagata (Kobe University), Sylvain Guilley (Secure-IC) ISEC2019-3
In this talk, we introduce the paper “Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology” by Je... [more] ISEC2019-3
p.5
MW, ICD 2019-03-14
13:00
Okinawa   Measurement of Undesired Radio W aves from Inverter Power D evices and Interference on Mobile C ommunications.
Yoshifumi Sugimoto, Koh Watanabe, Makoto Nagata, Noriyuki Miura (Kobe Univ.), Yasunori Miyazawa, Satoshi Tanaka, Masahiro Yamaguchi (Tohoku Univ.) MW2018-160 ICD2018-104
(To be available after the conference date) [more] MW2018-160 ICD2018-104
pp.23-25
MW, ICD 2019-03-15
11:25
Okinawa   Measurement of electromagnetic noise’s injection locking of on-chip LC oscillator and its application
Yue Cheng, Kou Watanabe, Noriyuki Miura, Makoto Nagata (Kobe Univ.) MW2018-173 ICD2018-117
 [more] MW2018-173 ICD2018-117
pp.93-95
HWS, VLD 2019-03-01
14:30
Okinawa Okinawa Ken Seinen Kaikan Integrated Circuit Design and Evaluation of Chip-Package-Board Interactive PUF Based on Wireless Chaos Oscillation
Masanori Takahashi, Makoto Nagata, Noriyuki Miura (Kobe Univ.) VLD2018-130 HWS2018-93
We proposed chip-package-board interactive PUF using chaos oscillation that is compatible with wireless coupling as a co... [more] VLD2018-130 HWS2018-93
pp.223-224
HWS, VLD 2019-03-02
10:00
Okinawa Okinawa Ken Seinen Kaikan An ultra-light weight implementation of PRINCE-family cryptographic processor
Kohei Matsuda, Makoto Nagata, Noriyuki Miura (Kobe Univ.) VLD2018-137 HWS2018-100
An ultra-light-weight PRINCE cryptographic processor was proposed by Miura, et al. in 2017.
In this paper, based on thi... [more]
VLD2018-137 HWS2018-100
pp.261-265
HWS, VLD 2019-03-02
10:25
Okinawa Okinawa Ken Seinen Kaikan ASIC Chip Implementation and Evaluation of Elliptic Curve Digital Signature Algorithm
Sosuke Sato, Hiroki Yoshida, Kazuki Monta (Kobe Univ.), Takaaki Okidono (ECSEC), Takuji Miki, Noriyuki Miura, Makoto Nagata (Kobe Univ.) VLD2018-138 HWS2018-101
We have designed and fabricated application specific semiconductor integrated circuit (ASIC) chips that embody the gener... [more] VLD2018-138 HWS2018-101
pp.267-269
ICD, CPSY, CAS 2018-12-23
09:30
Okinawa   [Poster Presentation] Evaluation of side-channel leakage in crypto modules with On-Chip-Monitor
Kazuki Monta, Hiroki Sonoda, Akihiro Tsukioka (Kobe Univ.), Takaaki Okidono (ECSEC), Takuji Miki, Noriyuki Miura, Makoto Nagata (Kobe Univ.) CAS2018-103 ICD2018-87 CPSY2018-69
 [more] CAS2018-103 ICD2018-87 CPSY2018-69
p.101
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-07
14:35
Hiroshima Satellite Campus Hiroshima Analysis of Conductive Power Noise Characteristics in Digital IC Chips between two Different IC Packaging Structures
Akihiro Tsukioka, Kosuke Jike, Koh Watanabe, Noriyuki Miura, Makoto Nagata (Kobe Univ.) CPM2018-96 ICD2018-57 IE2018-75
The conducted and radiated emission are caused by the dynamic power consumption in digital circuit operations. The chara... [more] CPM2018-96 ICD2018-57 IE2018-75
pp.37-42
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