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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM 2012-03-05
15:25
Tokyo Kikai-Shinko-Kaikan Bldg. Influence of Via Stress on Surface Micro-roughness-induced Leakage Current in Through-Silicon Via Interconnects
Hideki Kitada (Univ. of Tokyo/Fujitsu Lab.), Nobuhide Maeda, Koji Fujimoto, Shoichi Kodama, Young Suk Kim (Univ. of Tokyo), Yoriko Mizushima (Univ. of Tokyo/Fujitsu Lab.), Tomoji Nakamura (Fujitsu Lab.), Takayuki Ohba (Univ. of Tokyo) SDM2011-183
 [more] SDM2011-183
pp.41-46
SDM 2011-02-07
15:25
Tokyo Kikai-Shinko-Kaikan Bldg. Development of Low Temperature Bump-less TSV Process in 3D Stacking Technology
Hideki Kitada, Nobuhide Maeda (The Univ. of Tokyo), Koji Fujimoto (Dai Nippon Printing), Yoriko Mizushima, Yoshihiro Nakata, Tomoji Nakamura (Fujitsu Laboratories Ltd.), Takayuki Ohba (The Univ. of Tokyo) SDM2010-224
Diffusion behavior of Cu in Cu through-silicon-vias (TSVs) fabricated using low-temperature plasma enhanced chemical vap... [more] SDM2010-224
pp.49-53
ICD, SDM 2010-08-27
10:15
Hokkaido Sapporo Center for Gender Equality [Invited Talk] Development of sub-10um Thinning Technology using Actual Device Wafers
Nobuhide Maeda, Kim Youngsuk (Univ. of Tokyo), Yukinobu Hikosaka, Takashi Eshita (FSL), Hideki Kitada, Koji Fujimoto (Univ. of Tokyo), Yoriko Mizushima (Fujitsu Labs.), Kousuke Suzuki (DNP), Tomoji Nakamura (Fujitsu Labs.), Akihito Kawai, Kazuhisa Arai (DISCO), Takayuki Ohba (Univ. of Tokyo) SDM2010-141 ICD2010-56
200-mm and 300-mm device wafers were successfully thinned down to less than 10-μm. A 200-nm non-crystalline layer remain... [more] SDM2010-141 ICD2010-56
pp.95-97
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