Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 10:45 |
Oita |
B-ConPlaza |
A hardware description method and sematics providing a timing constrant Shunji Nishimura, Motoki Amagasaki, Toshinori Sueyoshi (Kumamoto Univ.) VLD2014-82 DC2014-36 |
Formal verification methods are wide-spreading due to its mathmatical rigorousaspect, although they limited to synchroun... [more] |
VLD2014-82 DC2014-36 pp.81-86 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-27 16:00 |
Oita |
B-ConPlaza |
Design and Evaluation of High-speed Serial Communication Mechanism for FPGA-based ASIC Emulator Takashi Okamoto, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-42 |
The circuit scale of Application Specific Integrated Circuit(ASIC)has been increasing. Therefore the shortening of funct... [more] |
RECONF2014-42 pp.45-50 |
RECONF |
2014-09-18 14:10 |
Hiroshima |
|
Prototype of fault tolerant FPGA using 65nm CMOS process Motoki Amagasaki, Takuya Kajiwara, Kentaro Fujisawa, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-18 |
我々はSoC(System on a Chip)に搭載されるFPGA-IP(Field Programmable Gate Array Intellectual
Property)コアに焦点をあてたFT-FPGA(Fault Tolera... [more] |
RECONF2014-18 pp.7-12 |
RECONF |
2014-09-18 14:35 |
Hiroshima |
|
A study of run-time fault detection mechanism for fault-tolerant FPGAs Kentaro Fujisawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-19 |
The fault detection is very important for high reliability system LSI. In this paper, we propose a dynamic fault detecti... [more] |
RECONF2014-19 pp.13-18 |
RECONF |
2014-09-19 14:40 |
Hiroshima |
|
Formal Verification System of Multi-clock Synchronous Circuits on Multimodal Logic Shunji Nishimura, Motoki Amagasaki, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-33 |
Regardless of wide using of a formal verification methods, almost all of the methods limited to single-clock synchrounou... [more] |
RECONF2014-33 pp.93-98 |
RECONF |
2014-06-12 11:15 |
Miyagi |
Katahira Sakura Hall |
Three-dimensional FPGA Structure using High-speed Serial Communication Takuya Kajiwara, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-7 |
The three-dimensional (3D) integrated circuit technology is expected to continually improve the LSI (Large Scale Integra... [more] |
RECONF2014-7 pp.31-36 |
RECONF |
2014-06-12 14:10 |
Miyagi |
Katahira Sakura Hall |
Zyndroid: HW/SW Coprocessing Platform for Android Applications Susumu Mashimo, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-10 |
Nowadays, high performance of Android systems is required because the embedded systems are used in several fields and th... [more] |
RECONF2014-10 pp.49-54 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 08:55 |
Kagoshima |
|
Mapping of Java bytecode to virtual CGRA with implementation in FPGA Yuki Ogawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2013-47 |
In embedded systems, the needs for rapid both low-cost development and high performance has been increasing recently.
... [more] |
RECONF2013-47 pp.45-50 |
RECONF |
2013-09-19 09:25 |
Ishikawa |
Japan Advanced Institute of Science and Technology |
A LUT Architecture Based on Partial Function of Shannon Expansion Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2013-27 |
In order to implement logic functions, conventional eld programmable gate arrays (FPGAs) employs look-up tables (LUTs) ... [more] |
RECONF2013-27 pp.43-48 |
SIP, CAS, MSS, VLD |
2013-07-11 18:00 |
Kumamoto |
Kumamoto Univ. |
SOM Based FPGA Placement Method Considering Wire Segment Length Tetsuro Hamada, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) CAS2013-16 VLD2013-26 SIP2013-46 MSS2013-16 |
A placement process is one of the heavily computational process in FPGA(Field Programmable Gate Array) design flow.
Al... [more] |
CAS2013-16 VLD2013-26 SIP2013-46 MSS2013-16 pp.83-88 |
RECONF |
2013-05-21 10:10 |
Kochi |
Kochi Prefectural Culture Hall |
Design and Evaluation of FPGA-based ASIC Emulator using High-speed Serial Communication Takashige Uda, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2013-10 |
Recently, development period of ASIC is longer becouse of the increase in circuit scale.
Verification process accounts ... [more] |
RECONF2013-10 pp.49-54 |
RECONF |
2013-05-21 11:25 |
Kochi |
Kochi Prefectural Culture Hall |
A defect-robust FPGA-IP core architecture Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2013-13 |
In this paper, we propose fault-tolerant FPGA -IP cores for system LSI. Unlike discrete FPGAs, in
which the integration... [more] |
RECONF2013-13 pp.67-72 |
CPSY, VLD, RECONF, IPSJ-SLDM [detail] |
2013-01-16 10:00 |
Kanagawa |
|
A Study of 3D FPGA Architecture Using Face-to-Face Stacked Routing Layer Yusuke Iwai, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2012-109 CPSY2012-58 RECONF2012-63 |
3D LSIs promise More than Moore integration by packing a great deal of functionality on a chip, while improving performa... [more] |
VLD2012-109 CPSY2012-58 RECONF2012-63 pp.13-18 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 14:15 |
Fukuoka |
Centennial Hall Kyushu University School of Medicine |
A study on reconfigurable direct conversion JAVA accelerator for embedded systems Seiya Takada, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ) RECONF2012-48 |
In embedded systems, the requirements for short-time and low-cost development have been increased
recently. For this re... [more] |
RECONF2012-48 pp.9-14 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 09:00 |
Fukuoka |
Centennial Hall Kyushu University School of Medicine |
A Basic Study of FPGA Routing Architecture Based on Scale Free Network Satoshi Hayama, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2012-50 |
FPGA(Fiele Programmable Gate Array) has many routing resources in order to provide the flexibility.
These routing resou... [more] |
RECONF2012-50 pp.17-22 |
RECONF |
2012-09-18 15:15 |
Shiga |
Epock Ritsumei 21, Ritsumeikan Univ. |
An Area Minimized Logic Cluster using COGRE Logic Cell Toshiya Takahashi, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2012-32 |
These days, FPGAs (Field Programmable Gate Arrays) is required to increase in size and performance
in order to deal w... [more] |
RECONF2012-32 pp.49-54 |
RECONF |
2012-09-19 13:15 |
Shiga |
Epock Ritsumei 21, Ritsumeikan Univ. |
A Design Framework for Reconfigurable IPs with VLSI CADs Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2012-41 |
The conventional FPGA design CAD flows evaluate FPGA architecture by implementing benchmarks through the following steps... [more] |
RECONF2012-41 pp.101-106 |
RECONF |
2012-09-19 15:05 |
Shiga |
Epock Ritsumei 21, Ritsumeikan Univ. |
Speedup of soft error tolerance evaluation with bootstrap method for FPGA systems Kohei Takano, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2012-45 |
SRAM-based field programmable gate arrays (FPGAs) are vulnerable to a single event upset (SEU). Although techniques for ... [more] |
RECONF2012-45 pp.125-130 |
DC, CPSY (Joint) |
2012-08-03 09:30 |
Tottori |
Torigin Bunka Kaikan |
A development scheduling simulater for reconfiguable system Takashige Uda, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) CPSY2012-19 |
Reconfigurable Computing Systems (RC Systems) are used to high-speed applications processing. We have investigating the ... [more] |
CPSY2012-19 pp.61-66 |
RECONF |
2012-05-29 15:10 |
Okinawa |
Tiruru (Naha Okinawa, Japan) |
Hard error avoidance for TMR module using dynamic relocation in an FPGA Hiroki Tanaka, Yoshihiro Ichinomiya, Sadaki Usagawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2012-11 |
FPGA can recover from hard-error by reconfiguring itself, avoiding the hard-error part.Especially, the fault recovery ca... [more] |
RECONF2012-11 pp.61-66 |