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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2021-02-05 14:00 |
Online | Online | Multiple Target Test Generation Method using Test Scheduling Information of RTL Hardware Elements Ryuki Asami, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ), Masayuki Arai (Nihon Univ)  DC2020-74 |
In recent years, since the test cost for large-scale integrated circuits has increased, design-for-testability methods f... [more] | DC2020-74 pp.30-35 |
| DC, CPSY, IPSJ-ARC [detail] | 2020-10-12 15:20 |
Online | Online | Note on CNN-Based Defect Location Estimation on LSI Layouts Yoshikazu Nagamura (Tokyo Metro. Univ.), Masayuki Arai (Nihon Univ.), Satoshi Fukumoto (Tokyo Metro. Univ.) CPSY2020-20 DC2020-20 |
[more] | CPSY2020-20 DC2020-20 pp.16-21 |
| CPSY, DC, IPSJ-ARC [detail] | 2020-07-31 15:45 |
Online | Online | A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the number of Test Patterns Ryuki Asami, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.) CPSY2020-12 DC2020-12 |
In recent years, as the high density and complexity of integrated circuits have increased, defects in cells have increas... [more] | CPSY2020-12 DC2020-12 pp.75-80 |
| HWS, VLD [detail] | 2020-03-06 14:30 |
Okinawa | Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
A Test Generation Method for Resistive Open Faults Using Partial MAX-SAT solver Hiroshi Yamazaki, Yuta Ishiyama, Tatsuma Matsuta, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2019-131 HWS2019-104 |
In VLSI testing, stuck-at fault model and transition fault model have been widely used. However, with advance of semicon... [more] | VLD2019-131 HWS2019-104 pp.215-220 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2020-02-27 14:30 |
Kagoshima | Yoron-cho Chuou-Kouminkan | Note on Dependable LoRa Transmission by Frequency and Gateway Multiplexing Kohei Kudo, Kazuki Sasaki, Masayuki Arai (Nihon Univ.) CPSY2019-98 DC2019-104 |
Recently, LPWA (Low Power Wide Area) is attracting the attention as IoT-oriented communication technology, which enables... [more] | CPSY2019-98 DC2019-104 pp.63-68 |
| DC | 2020-02-26 14:10 |
Tokyo | A Don’t Care Identification-Filling Co-Optimization Method for Low Power Testing Using Partial Max-SAT Kenichiro Misawa, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyouto Sangyo Univ), Masayuki Arai (Nihon Univ) DC2019-92 |
Recently, in at-speed scan testing, excessive capture power dissipation is a serious problem. Low capture power test gen... [more] | DC2019-92 pp.37-42 |
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| DC, CPSY, IPSJ-ARC [detail] | 2019-06-11 14:50 |
Kagoshima | National Park Resort Ibusuki | Note on Fast SAT-Based SDN Rule Table Partitioning Ryota Ogasawara, Masayuki Arai (Nihon Univ.) CPSY2019-4 DC2019-4 |
[more] | CPSY2019-4 DC2019-4 pp.39-44 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2019-03-18 09:00 |
Kagoshima | Nishinoomote City Hall (Tanega-shima) | A Test Generation Method for Resistive Open Faults Using MAX-SAT Problem Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) CPSY2018-117 DC2018-99 |
In VLSI testing, stuck-at fault model and transition fault model have been widely used. However, with advance of semicon... [more] | CPSY2018-117 DC2018-99 pp.315-320 |
| DC | 2019-02-27 09:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Note on Target Fault Selection for 2-Pattern Test Generation Considering Critical Area Naoya Uchiyama, Masayuki Arai (Nihon Univ.) DC2018-71 |
[more] | DC2018-71 pp.1-5 |
| DC | 2018-12-14 14:05 |
Okinawa | Miyako Seisyonen-No-Ie | SAT-Based Solution for SDN Rule Table Partitioning Ryota Ogasawara, Masayuki Arai (Nihon Univ.) DC2018-61 |
[more] | DC2018-61 pp.19-23 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 10:55 |
Hiroshima | Satellite Campus Hiroshima | On the Generation of Random Capture Safe Test Vectors Using Neural Networks Sayuri Ochi, Kenichirou Misawa, Toshinori Hosokawa, Yukari Yamauchi, Masayuki Arai (Nihon Univ.) VLD2018-51 DC2018-37 |
Excessive capture power consumption at scan testing causes the excessive IR drop and it might cause test-induced yield l... [more] | VLD2018-51 DC2018-37 pp.89-94 |
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2018-07-30 17:30 |
Kumamoto | Kumamoto City International Center | Note on Reliability Improvements of BAN by Delay Tolerant Networking Tomoyuki Kirii, Masayuki Arai (Nihon Univ.) DC2018-16 |
[more] | DC2018-16 pp.19-22 |
| CPSY, DC, IPSJ-ARC [detail] | 2018-06-15 13:50 |
Yamagata | Takamiya Rurikura Resort | Note on Real-Time Wireless Data Transmission for Power Electronics Systems Shingo Yokoyama, Mamoru Ohara (Tokyo Metro. Univ.), Masayuki Arai (Nihon Univ.) CPSY2018-8 DC2018-8 |
In a power electronics circuit, voltage and current are measured by a sensor inside the circuit. Measurement with wired ... [more] | CPSY2018-8 DC2018-8 pp.119-124 |
| CPSY, DC, IPSJ-ARC [detail] | 2018-06-15 14:20 |
Yamagata | Takamiya Rurikura Resort | Study on Privacy-Preserving k-Fault-Tolerant Data Aggregation on Smart Grid Communications Hiroki Saito, Ryota Ogasawara, Masayuki Arai (Nihon Univ.) CPSY2018-9 DC2018-9 |
[more] | CPSY2018-9 DC2018-9 pp.125-130 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2018-03-08 15:00 |
Shimane | Okinoshima Bunka-Kaikan Bldg. | A Study of Response Time Analysis of Controller Area Networks Ryouhei Satoh, Kazuya Sakai, Satoshi Fukumoto, Mamoru Ohara (Tokyo Metropolitan Univ.), Masayuki Arai (Nihon Univ.) CPSY2017-148 DC2017-104 |
A number of methods have been proposed for response time analysis of CAN, which is an industry standard of in-vehicle ne... [more] | CPSY2017-148 DC2017-104 pp.269-274 |
| DC | 2018-02-20 09:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Note on Weighted Fault Coverage for Two-Pattern Tests Masayuki Arai (Nihon Univ.), Kazuhiko Iwasaki (Tokyo Metro. Univ.) DC2017-77 |
hrinking feature size and higher integration on semiconductor device manufacturing technology bring a problem of the gap... [more] | DC2017-77 pp.1-6 |
| RECONF, CPSY, DC, IPSJ-ARC (Joint) [detail] |
2017-05-24 12:10 |
Hokkaido | Noboribetsu-Onsen Dai-ichi-Takimoto-Kan | Note on Evaluation Scheme for Redundant CPU Cache Considering Soft Error Resilience and Performance Naoya Kawashima, Masayuki Arai (Nihon Univ.) CPSY2017-15 DC2017-15 |
[more] | CPSY2017-15 DC2017-15 pp.103-106 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2017-03-10 09:50 |
Okinawa | Kumejima Island | A Note on Analytical Models for CANs Ryohei Satoh, Kazuya Sakai, Satoshi Fukumoto (Tokyo Metropolitan Univ.), Masayuki Arai (Nihon Univ.), Mamoru Ohara (Tokyo Metropolitan Univ.) CPSY2016-145 DC2016-91 |
In recent years, the controller area networks (CANs), the industry standard of in-vehicle network protocol, have continu... [more] | CPSY2016-145 DC2016-91 pp.297-301 |
| DC | 2017-02-21 10:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A dynamic test compaction method on low power oriented test generation using capture safe test vectors Toshinori Hosokawa, Atsushi Hirai, Hiroshi Yamazaki, Masayuki Arai (Nihon Univ.) DC2016-74 |
In at-speed scan testing, capture power is a serious problem because the high power dissipation that can occur when the ... [more] | DC2016-74 pp.1-6 |
| DC | 2017-02-21 14:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An Untestable Fault Identification Method for Sequential Circuits Based on SAT Using Unreachable States Morito Niseki, Toshinori Hosokawa (Nihon Univ.), Msayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) DC2016-79 |
Scan design has problems such as large hardware overhead and long test application time. Non-scan based test generation ... [more] | DC2016-79 pp.29-34 |
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