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Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF 2010-09-16
16:35		 Shizuoka Shizuoka University (Faculty of Eng., Hall 2) Design and Implementation of a Layout Tool for the MPLD Architecture
Ken Taomoto, Hideyuki Kawabata, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.), Masayuki Sato, Takashi Ishiguro (Taiyo Yuden), Toshiaki Kitamura (Hiroshima City Univ.) RECONF2010-27		 A rapidly and partially reconfigurable fine-grain programmable logic device, named MPLD, has been proposed. The MPLD arc... [more] RECONF2010-27
pp.55-60
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-27
13:05		 Kanagawa Keio Univ (Hiyoshi Campus) Regular Expression Pattern Matching Hardware for Realizing Iteration of Strings Using Quantifiers
Yoichi Wakaba, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi (Hiroshima City Univ) VLD2009-91 CPSY2009-73 RECONF2009-76		 Regular expression pattern matching is a problem to find substrings in a given text，which match with a pattern represent... [more] VLD2009-91 CPSY2009-73 RECONF2009-76
pp.137-142
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-29
13:45		 Kanagawa   Circuit Partition Method with Time-multiplexed I/O
Tatsuki Isomura (Univ. of Kitakyushu), Masato Inagi (Hiroshima City Univ.), Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC) VLD2008-100 CPSY2008-62 RECONF2008-64		 We propose a partition method to prototype a large scaled system with time-multiplexed I/Os. Recent prototyping of a lar... [more] VLD2008-100 CPSY2008-62 RECONF2008-64
pp.51-55
CAS, SIP, VLD 2007-06-22
13:40		 Hokkaido Hokkaido Tokai Univ. （Sapporo) Optimization of Time-Multiplexed I/O Assignment in Multi-FPGA Systems
Masato Inagi, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC) CAS2007-28 VLD2007-44 SIP2007-58		 Recently, integrated circuit design size and complexity have been increasing rapidly. FPGA systems are used to
verify s... [more]		 CAS2007-28 VLD2007-44 SIP2007-58
pp.55-60
ICD, VLD 2007-03-08
13:30		 Okinawa Mielparque Okinawa Escape Fitting between a Pair of Pin-Sets
Masato Inagi, Yasuhiro Takashima, Yoji Kajitani (Univ. of Kitakyushu) 		 [more] VLD2006-130 ICD2006-221
pp.67-72
ICD, VLD 2007-03-08
13:50		 Okinawa Mielparque Okinawa BGA Routing by The Potential Router
Takayuki Hiromatsu, Masato Inagi, Yasuhiro Takashima, Yoji Kajitani (Univ. of Kitakyushu) 		As the number of devices in an LSI chip becomes larger, the number of package pins also becomes larger. To fold the pins... [more] VLD2006-131 ICD2006-222
pp.73-78
CAS 2007-01-30
10:20		 Ehime Ehime Univ. A Circuit Partitioning Algorithm for Multi-FPGA Systems with Time-multiplexed I/Os
Masato Inagi, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC) 		 [more] CAS2006-72
pp.13-17
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