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 Results 21 - 32 of 32 [Previous]  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
IE, ICD, VLD, IPSJ-SLDM [detail] 2013-10-07
10:55		 Aomori   Proposal of Double-clock and Dual-Edge-Triggered Flip-flops for Asynchronous Circuits
Masashi Imai (Hirosaki Univ.), Tomohiro Yoneda (NII) VLD2013-47 ICD2013-71 IE2013-47		 There are mainly two types of handshaking protocols in asynchronous circuit design; 2-phase handshaking protocol and 4-p... [more] VLD2013-47 ICD2013-71 IE2013-47
pp.7-12
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2010-11-30
10:10		 Fukuoka Kyushu University A study of high-performance asynchronous network-on-chip focused on bias of packets transfer routes
Satoshi Takeyasu, Masashi Imai, Hiroshi Nakamura (Tokyo Univ.) VLD2010-66 DC2010-33		 GALS-NoC is recently paid attention. Beside, NoC have commonly bias of packets transfer routes by regularity of network ... [more] VLD2010-66 DC2010-33
pp.67-72
DC 2010-10-14
15:50		 Tokyo Kikai-Shinko-Kaikan Bldg [Invited Talk] Report of DSN2010(The 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks)
Masashi Imai (Univ. of Tokyo) DC2010-23		  [more] DC2010-23
pp.31-34
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2009-12-03
10:40		 Kochi Kochi City Culture-Plaza An Approach to Dependable Chip Multiprocessors with Process Pair and Swap Mechanism
Tomohide Nagai, Masashi Imai, Takashi Nanya (Univ. of Tokyo) VLD2009-51 DC2009-38		 With the down scale of technology and the increase of transistor count, future processors are expected to be more suscep... [more] VLD2009-51 DC2009-38
pp.67-72
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2008-11-19
11:15		 Fukuoka Kitakyushu Science and Research Park Leakage Power Reduction Method for Dual-Rail Four-Phase Asynchronous Circuits Using Multi-Vth Transistors
Koei Takada, Masashi Imai, Hiroshi Nakamura, Takashi Nanya (U. of Tokyo) VLD2008-90 DC2008-58		 Dual-rail four-phase asynchronous circuits are well-known for their benefits in terms of delay variation tolerance. On t... [more] VLD2008-90 DC2008-58
pp.183-188
DC, CPSY 2008-04-23
16:45		 Tokyo Tokyo Univ. An approach to tolerating delay faults based on asynchronous circuits
Tomohiro Yoneda (NII), Masashi Imai (Univ. of Tokyo), Atsushi Matsumoto, Takahiro Hanyu (Tohoku Univ.), Yuichi Nakamura (NEC) CPSY2008-10 DC2008-10		 Recent advances in semiconductor process technologies cause new types of faults, which should be handled in order to obt... [more] CPSY2008-10 DC2008-10
pp.55-60
EA, US
(Joint)		 2008-01-29
15:15		 Osaka Kansai University Process of evolutionary reformation of a photoacoustic microscope system
Yoshiaki Tokunaga, Hiroyuki Kobayashi, Masashi Imai (Kanazawa Inst. Tech) US2007-105		 Evolutionary reformation from a compact photoacoustic microscope to a laser induced thermal wave microscope system(LITWM... [more] US2007-105
pp.49-52
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]		 2007-11-20
10:55		 Fukuoka Kitakyushu International Conference Center A process-variation-aware low-power technique using current control
Kyun-dong Kim, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya (Univ. of Tokyo) VLD2007-76 DC2007-31		 Due to process variations, the difference of the operation speed between pipeline stages is increased,resulting in a num... [more] VLD2007-76 DC2007-31
pp.37-42
ICD, IPSJ-ARC 2007-06-01
13:15		 Kanagawa   The Concept of Innovative Power Control for Ultra Low-Power and High-Performance System LSIs
Hiroshi Nakamura (Univ. of Tokyo), Hideharu Amano (Keio Univ.), Kimiyoshi Usami (Shibaura Inst. Tech.), Mitaro Namiki (TUAT), Masashi Imai, Masaaki Kondo (Univ. of Tokyo) 		 [more] ICD2007-30
pp.79-84
ICD, SDM 2006-08-17
10:20		 Hokkaido Hokkaido University Low power delay-insensitive asynchronous curcuits using 1-out-of-4 encoding.
Tomohiro Fujii, Masashi Imai, Hiroshi Nakamura, Takashi Nanya (Univ. of Tokyo) 		 [more] SDM2006-128 ICD2006-82
pp.19-24
VLD, ICD, DC, IPSJ-SLDM 2005-11-30
16:35		 Fukuoka Kitakyushu International Conference Center A Discussion about Timing Signal Design Considering Delay Variation
Masashi Imai, Kouichi Watanabe, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya (Univ. Tokyo) 		As the VLSI technology advances, delay variations become extremely
large. There are many factors that cause delay varia... [more]		 VLD2005-59 ICD2005-154 DC2005-36
pp.31-36
VLD, ICD, DC, IPSJ-SLDM 2005-11-30
17:00		 Fukuoka Kitakyushu International Conference Center Design of High Performance and Low Power Arithmetic Circuits Considering Bit Delay Variation
Kouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya (Univ. Tokyo) 		As the VLSI technology advances, delay variations will become more serious.
Delay insensitive asynchronous dual-rail ci... [more]		 VLD2005-60 ICD2005-155 DC2005-37
pp.37-42
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