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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 12:05 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Data-dependent Approximation-circuit Design using Timing-error Prediction Scheme and its Evaluations on FPGA Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)  VLD2015-66 DC2015-62 |
The propagation delay and the transition probability along each path inside an LSI widely vary depending on input data, ... [more] | VLD2015-66 DC2015-62 pp.183-188 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 15:00 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Circuit Area-Aware Bit-Write Reduction Code Generation for Non-Volatile Memories Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-76 DC2015-72 |
Recently, due to low leakage power and non-volatility, the non-volatile memory technology has advanced remarkably. Howe... [more] |
VLD2015-76 DC2015-72 pp.249-253 |
| VLD, IPSJ-SLDM | 2015-05-14 11:35 |
Fukuoka | Kitakyushu International Conference Center | Control Signal Extraction for Sequential Clock Gating Using Time Expansion of Sequential Circuits Tomoya Goto, Kohei Higuchi, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2015-4 |
Recently, clock gating is utilized as a method for reducing the dynamic power of LSI. Clock gating can be automatically... [more] |
VLD2015-4 pp.31-36 |
| VLD, IPSJ-SLDM | 2015-05-14 15:25 |
Fukuoka | Kitakyushu International Conference Center | AES Encryption Circuit against Clock Glitch based Fault Analysis Daisuke Hirano, Youhua Shi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ) VLD2015-7 |
Recently, fault analysis has attracted a lot of attentions as a new kind of side channel attack methods,in which malicio... [more] | VLD2015-7 pp.51-55 |
| VLD | 2015-03-03 09:15 |
Okinawa | Okinawa Seinen Kaikan | A low-power soft error tolerant latch scheme Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ.) VLD2014-162 |
In recent technology scaling, reduction of reliability by soft-error and increase power has appeared as an inevitable pr... [more] | VLD2014-162 pp.55-60 |
| VLD | 2015-03-03 16:15 |
Okinawa | Okinawa Seinen Kaikan | [Memorial Lecture]
A Bit-Write Reduction Method based on Error-Correcting Codes for Non-Volatile Memories Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-173 |
Non-volatile memory is superior to SRAM in terms of its high density and low leakage power but it consumes larger writ... [more] |
VLD2014-173 p.115 |
| VLD | 2015-03-04 13:25 |
Okinawa | Okinawa Seinen Kaikan | A Score-Based Hardware-Trojan Identification Method for Gate-Level Netlists Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-182 |
Recently, digital ICs are designed by outside vendors to reduce costs in semiconductor industry. This circumstance intr... [more] |
VLD2014-182 pp.165-170 |
| RECONF, CPSY, VLD, IPSJ-SLDM [detail] | 2015-01-30 10:50 |
Kanagawa | Hiyoshi Campus, Keio University | A Hardware Trojan Detection Method based on Trojan net features Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-137 CPSY2014-146 RECONF2014-70 |
Recently, digital ICs are designed by outside vendors to reduce costs in semiconductor industry. This circumstance intr... [more] |
VLD2014-137 CPSY2014-146 RECONF2014-70 pp.157-162 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 09:15 |
Oita | B-ConPlaza | Design of Flip-Flop with Timing Error Tolerance Taito Suzuki, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (SIT), Masao Yanagisawa (Waseda Univ.) VLD2014-79 DC2014-33 |
Under the influence of the miniaturization of the integrated circuit, the variation of the operation condition of the ci... [more] | VLD2014-79 DC2014-33 pp.45-50 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 09:40 |
Oita | B-ConPlaza | Data Dependent Optimization using Suspicious Timing Error Prediction for Reconfigurable Approximation Circuits Kazushi Kawamura, Shin-ya Abe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-80 DC2014-34 |
The propagation delay along each path inside an LSI widely varies depending on input data, and this property can be expl... [more] | VLD2014-80 DC2014-34 pp.51-56 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 10:05 |
Oita | B-ConPlaza | An Effective Robust Design Using Improved Checkpoint Insertion Algorithm for Suspicious Timing-Error Prediction Scheme and its Evaluations Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-81 DC2014-35 |
As process technologies advance, process and delay variation causes a complex timing design and in-situ timing error cor... [more] | VLD2014-81 DC2014-35 pp.57-62 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 14:45 |
Oita | B-ConPlaza | A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay Characteristics in FPGA Designs Koichi Fujiwara, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-85 DC2014-39 |
Recently, high-level synthesis (HLS) techniques for FPGA designs are required such as in image pro- cessing and computer... [more] | VLD2014-85 DC2014-39 pp.99-104 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 15:10 |
Oita | B-ConPlaza | A Process-Variation-Tolerant and Low-Latency Multi-Scenario High-level Synthesis Algorithm for HDR Architectures Koki Igawa, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-86 DC2014-40 |
In this paper, we propose a process-variation-tolerant and low-latency multi-scenario high-level synthesis algorithm for... [more] | VLD2014-86 DC2014-40 pp.105-110 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 16:15 |
Oita | B-ConPlaza | High speed design of sub-threshold circuit by using DTMOS Yuji Fukudome, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech), Masao Yanagisawa (Waseda Univ.) VLD2014-88 DC2014-42 |
Low power consumption is achieved by operating circuits in sub-threshold region. However, in sub-threshold region, the... [more] |
VLD2014-88 DC2014-42 pp.117-121 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 17:30 |
Oita | B-ConPlaza | A Hardware Trojans Detection Method focusing on Nets in Hardware Trojans in Gate-Level Netlists Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-91 DC2014-45 |
Recently, digital ICs are designed by outside vendors to reduce design costs in semiconductor industry. This circumstan... [more] |
VLD2014-91 DC2014-45 pp.135-140 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 15:10 |
Oita | B-ConPlaza | A Field Data Extractor Configuration Based on Multiplexer Tree Partitioning Koki Ito, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.), Yutaka Tamiya (Fujitsu Lab.) VLD2014-101 DC2014-55 |
As seen in packet analysis of TCP/IP offload engine and stream data processing of encoder/decoder for video data, it is ... [more] | VLD2014-101 DC2014-55 pp.197-202 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 15:35 |
Oita | B-ConPlaza | Energy-efficient High-level Synthesis Algorithm targeting HDR-mcv Architecture with Multiple Clock Domains and Multiple Supply Voltages Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Institute of Technology/Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-102 DC2014-56 |
An HDR-mcv architecture, which integrates multiple supply voltages and multiple clock domains into high-level synthesis ... [more] | VLD2014-102 DC2014-56 pp.203-208 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 16:00 |
Oita | B-ConPlaza | A High-level Synthesis Algorithm with Delay Variation Tolerance Optimization for RDR Architectures Yuta Hagio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-103 DC2014-57 |
In this paper, we propose a high-level synthesis algorithm with delay variation tolerance optimization for RDR architect... [more] | VLD2014-103 DC2014-57 pp.209-214 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 09:15 |
Oita | B-ConPlaza | Energy evaluation of bit-write reduction method based on state encoding limiting maximum and minimum Hamming distances for non-volatile memories Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-105 DC2014-59 |
Data stored in non-volatile memories may be destructed due to crosstalk and radiation but we can restore their data by u... [more] | VLD2014-105 DC2014-59 pp.221-226 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 09:40 |
Oita | B-ConPlaza | Small-Sized Encoder/Decoder Circuit Design for Bit-Write Reduction Targeting Non-Volatile Memories Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-106 DC2014-60 |
Non-volatile memory has many advantages such as low leakage power and non-volatility. However, there are problems that ... [more] |
VLD2014-106 DC2014-60 pp.227-232 |
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