| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IE, ITS, ITE-AIT, ITE-HI, ITE-ME, ITE-MMS, ITE-CE [detail] | 2017-02-21 14:00 |
Hokkaido | Hokkaido Univ. | (none) Ryota Iwanaji (Waseda Univ.), Tomoyuki Nitta (Zenrin DataCom), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)  ITS2016-71 IE2016-129 |
(To be available after the conference date) [more] | ITS2016-71 IE2016-129 pp.387-392 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-25 09:50 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Finite state machine design for high accurate stochastic computing Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2016-96 CPSY2016-132 RECONF2016-77 |
(To be available after the conference date) [more] | VLD2016-96 CPSY2016-132 RECONF2016-77 pp.171-174 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 09:50 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | FPGA Design and Evaluation of Selector-Logic-based Butterfly Unit Koki Ito, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2016-55 DC2016-49 |
(To be available after the conference date) [more] | VLD2016-55 DC2016-49 pp.67-72 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-30 11:20 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Malisious tamper detector design with capacitance measurement for IoT devices in operation Ryosuke Kitayama (Waseda Univ.), Takashi Takenaka (NEC), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2016-66 DC2016-60 |
(To be available after the conference date) [more] | VLD2016-66 DC2016-60 pp.129-134 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-30 13:20 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | An aging aware high-level synthesis algorithm with floorplanning Koki Igawa, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2016-68 DC2016-62 |
(To be available after the conference date) [more] | VLD2016-68 DC2016-62 pp.141-146 |
| VLD, CAS, MSS, SIP | 2016-06-16 09:30 |
Aomori | Hirosaki Shiritsu Kanko-kan | Hardware Trojan Identification based on Netlist Features using Neural Networks Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) CAS2016-1 VLD2016-7 SIP2016-35 MSS2016-1 |
(To be available after the conference date) [more] | CAS2016-1 VLD2016-7 SIP2016-35 MSS2016-1 pp.1-6 |
| VLD, CAS, MSS, SIP | 2016-06-16 09:50 |
Aomori | Hirosaki Shiritsu Kanko-kan | Verification Experiment of Scan-based Attack against a Trivium Cipher Circut Daisuke Oku, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) CAS2016-2 VLD2016-8 SIP2016-36 MSS2016-2 |
(To be available after the conference date) [more] | CAS2016-2 VLD2016-8 SIP2016-36 MSS2016-2 pp.7-12 |
| VLD, IPSJ-SLDM | 2016-05-11 14:30 |
Fukuoka | Kitakyushu International Conference Center | A High-Level Synthesis Algorithm using Critical Path Optimization Based Operation Chainings for RDR Architectures Kotaro Terada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2016-4 |
In deep-submicron era, interconnection delays are not negligible even in high-level synthesis. RDR (Regular Distributed ... [more] | VLD2016-4 pp.41-46 |
| VLD | 2016-03-01 09:50 |
Okinawa | Okinawa Seinen Kaikan | Evaluation of Rotator-based Multiplexer Network with Control Circuits for Field-data Extractors Koki Ito, Kazushi Kawamura (Waseda Univ.), Yutaka Tamiya (Fujitsu Lab.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-120 |
In this paper, we evaluate the number of gates required for rotator-based MUX network including control circuits. Experi... [more] | VLD2015-120 pp.55-60 |
| VLD | 2016-03-01 11:20 |
Okinawa | Okinawa Seinen Kaikan | Timing-error-tolerant AES Cipher Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-123 |
With the technologies advance, the importance of crypto circuits is increasing as well. AES cipher is well known as theo... [more] | VLD2015-123 pp.73-78 |
| VLD | 2016-03-01 11:45 |
Okinawa | Okinawa Seinen Kaikan | In-situ Hardware-Trojan Authentication for Invalidating Malicious Functions Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-124 |
[more] | VLD2015-124 pp.79-84 |
| VLD | 2016-03-01 15:10 |
Okinawa | Okinawa Seinen Kaikan | FPGA Implementation of a Distributed-register Architecture Circuit Using floorplan-aware High-level Synthesis Koichi Fujiwara, Kawamura Kazushi, Keita Igarashi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-127 |
Recently, high-level synthesis techniques for FPGA designs (FPGA-HLS) are much focused on such as in image processing an... [more] | VLD2015-127 pp.93-98 |
| VLD | 2016-03-02 09:00 |
Okinawa | Okinawa Seinen Kaikan | FPGA Design and Evaluation of Volume Rendering Circuits Using Selector Logic Keita Igarashi, Masao Yanagisawa, Togawa Nozomu (Waseda Univ.) VLD2015-132 |
[more] | VLD2015-132 pp.119-124 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-20 09:50 |
Kanagawa | Hiyoshi Campus, Keio University | Control Signal Extraction for Backward Sequential Clock Gating Tomoya Goto, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2015-89 CPSY2015-121 RECONF2015-71 |
[more] | VLD2015-89 CPSY2015-121 RECONF2015-71 pp.97-102 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-21 13:25 |
Kanagawa | Hiyoshi Campus, Keio University | A floorplan-driven high-level synthesis algorithm resilient to dynamic delay variations Koki Igawa, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-105 CPSY2015-137 RECONF2015-87 |
Recently, we have proposed a multi-scenario high-level synthesis algorithm targeting static process variations. The algo... [more] | VLD2015-105 CPSY2015-137 RECONF2015-87 pp.209-214 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-21 14:15 |
Kanagawa | Hiyoshi Campus, Keio University | Write-Reduction using Encoding data on MLC for Non-Volatile Memories Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-107 CPSY2015-139 RECONF2015-89 |
There is a movement to use the non-volatile memory to the important main memory in von Neumann computer. Non-volatile m... [more] |
VLD2015-107 CPSY2015-139 RECONF2015-89 pp.221-225 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 17:35 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay and Clock Skew in FPGA Designs Koichi Fujiwara, kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-54 DC2015-50 |
With recent process scaling in FPGAs, interconnection delays and clock skews have a large impact on the latency of a cir... [more] | VLD2015-54 DC2015-50 pp.99-104 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 15:55 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A low-power soft error tolerant latch scheme on 15nm process Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ.) VLD2015-56 DC2015-52 |
In recent technology scaling, reliability of integrated circuits due to a soft error is becoming more critical than ever... [more] | VLD2015-56 DC2015-52 pp.123-127 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 09:45 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Hardware Trojan Identification based on Netlist Features using SVM Kento Hasegawa, Oya Masaru, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-58 DC2015-54 |
Recently, third-party IC vendors are very often used due to globalization and cost-reduction in the IC market but malic... [more] |
VLD2015-58 DC2015-54 pp.135-140 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 10:10 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Quantitative Criterion of Gate-Level Netlist Vulnerability Masaru Oya, Youhua Shi (Waseda Univ.), Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo (NEC), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-59 DC2015-55 |
Recently, digital ICs are designed by outside vendors to reduce costs in semiconductor industry. This circumstance intr... [more] |
VLD2015-59 DC2015-55 pp.141-146 |
[Return to Top Page]