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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 7 of 7  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, SDM, ITE-IST [detail] 2022-08-08
09:15
Online   [Invited Talk] A 2-Layer Transistor Pixel Stacked CMOS Image Sensor with Oxide Based Full Trench Isolation for Large Full Well Capacity and High Quantum Efficiency
Koichiro Zaitsu, Akira Matsumoto, Mizuki Nishida, Yusuke Tanaka, Hirofumi Yamashita, Yosuke Satake (Sony Semiconductor Solutions), Takashi Watanabe, Kunihiko Araki, Naoki Nei (Sony Semiconductor Manufacturing), Keiichi Nakazawa, Junpei Yamamoto, Mutsuo Uehara (Sony Semiconductor Solutions), Hiroyuki Kawashima, Yusaku Kobayashi (Sony Semiconductor Manufacturing), Tomoyuki Hirano, Keiji Tatani (Sony Semiconductor Solutions) SDM2022-33 ICD2022-1
(To be available after the conference date) [more] SDM2022-33 ICD2022-1
pp.1-6
SDM 2022-02-04
11:20
Online Online [Invited Talk] 3D Sequential Process Integration for CMOS Image Sensor
Keiichi Nakazawa, Junpei Yamamoto, Nobutoshi Fujii, Mutsuo Uehara, Katsunori Hiramatsu, Hideomi Kumano, Shigetaka Mori, Shintaro Okamoto, Akito Shimizu, Koichi Baba, Hidetoshi Onuma, Akira Matsumoto, Koichiro Zaitsu, Keiji Tanani, Tomoyuki Hirano, Hayato Iwamoto (Sony Semiconductor Solutions) SDM2021-77
We developed a new structure of pixel transistors stacked over photodiode named “2-Layer Transistor Pixel Stacked CMOS I... [more] SDM2021-77
pp.13-16
SDM 2022-01-31
16:00
Online Online [Invited Talk] ****
Keiichi Nakazawa, Junpei Yamamoto, Shigetaka Mori, Shintaro Okamoto, Akito Shimizu, Koichi Baba, Nobutoshi Fujii, Mutsuo Uehara, Katsunori Hiramatsu, Hideomi Kumano, Akira Matsumoto, Koichiro Zaitsu, Hidetoshi Ohnuma, Keiji Tatani, Tomoyuki Hirano, Hayato Iwamoto (Sony Semiconductor Solutions) SDM2021-73
We developed a new structure of pixel transistors stacked over photodiode named “2-Layer Transistor Pixel Stacked CMOS I... [more] SDM2021-73
pp.20-23
ICD 2017-04-21
13:00
Tokyo   [Invited Lecture] High-Density User-Programmable Logic Array Based on Adjacent Integration of Pure-CMOS Crossbar Antifuse into Logic CMOS Circuits
Shinichi Yasuda, Masato Oda, Mari Matsumoto, Kosuke Tatsumura, Koichiro Zaitsu, Ying-Hao Ho, Mizuki Ono (Toshiba) ICD2017-15
 [more] ICD2017-15
pp.79-83
SDM 2015-10-29
16:30
Miyagi Niche, Tohoku Univ. [Invited Talk] Low-power and high-speed FPGA by adjacent integration of flash memory and CMOS logic
Koichiro Zaitsu, Kosuke Tatsumura, Mari Matsumoto, Masato Oda, Shinichi Yasuda (Toshiba) SDM2015-75
Novel nonvolatile programmable switch for low-power and high-speed FPGA where flash memory is adjacently integrated to C... [more] SDM2015-75
pp.23-28
ICD, SDM 2014-08-05
11:15
Hokkaido Hokkaido Univ., Multimedia Education Bldg. [Invited Talk] Low-Power and High-Speed Nonvolatile FPGA by Adjacent Integration of MONOS/Logic and Novel Programming Scheme
Koichiro Zaitsu, Kosuke Tatsumura, Mari Matsumoto, Masato Oda, Shinobu Fujita, Shinichi Yasuda (Toshiba) SDM2014-75 ICD2014-44
Novel nonvolatile programmable switch for low-power and high-speed FPGA where MONOS flash is adjacently integrated to CM... [more] SDM2014-75 ICD2014-44
pp.71-76
OME 2008-01-11
13:00
Tokyo Kikai-Shinko-Kaikan Bldg. Nonvolatile ferroelectric memories using organic transistor structures
Koichiro Zaitsu, Tsuyoshi Sekitani, Kiyoshiro Ishibe, Takao Someya (Univ. of Tokyo) OME2007-68
We have successfully fabricated air-stable organic nonvolatile memories comprising ferroelectric field-effect transistor... [more] OME2007-68
pp.1-6
 Results 1 - 7 of 7  /   
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