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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| MW (2nd) |
2017-06-14 - 2017-06-16 |
Overseas | KMUTT, Bangkok, Thailand | [Short Paper]
RF Characteristics of SOTB Devices for GHz Frequency Applications Van-Trung Nguyen, Koichiro Ishibashi (UEC) |
The paper presents RF characteristics of the 65nm SOTB CMOS devices for 1GHz range. With many superior features such as ... [more] | |
| SR | 2017-01-20 10:15 |
Ehime | Himegin Hall | A study on low-power sensor node using synchronous MAC protocol Shohei Ishigaki, Koichiro Ishibashi (UEC)  SR2016-86 |
[more] | SR2016-86 pp.45-52 |
| SDM | 2016-10-26 15:30 |
Miyagi | Niche, Tohoku Univ. | [Invited Talk]
Back-Bias Control Technique for Suppression of Die-to-Die Delay Variability of SOTB CMOS Circuits at Ultralow-Voltage (0.4 V) Operation Hideki Makiyama, Yoshiki Yamamoto, Takumi Hasegawa, Shinobu Okanishi, Keiichi Maekawa, Hiroki Shinkawata, Shiro Kamohara, Yasuo Yamaguchi (Renesas Electronics Corp.), Nobuyuki Sugii (Hitach), Koichiro Ishibashi (The Univ. of Electro-Communications), Tomoko Mizutani, Toshiro Hiramoto (The Univ. of Tokyo) SDM2016-71 |
Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation volta... [more] | SDM2016-71 pp.15-20 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 16:45 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | An implementation and preliminary evaluation of a dynamic body bias control scheme for a low power micro controller using SOTB MOSFET Hayate Okuhara (Keio Univ.), Tomoaki Koide (UEC), Johannes maximilian kuehn, Akram Ben Ahmed (Keio Univ.), Koichiro Ishibashi (UEC), Hideharu Amano (Keio Univ.) CPSY2015-71 |
[more] | CPSY2015-71 pp.57-62 |
| SDM | 2014-10-17 14:30 |
Miyagi | Niche, Tohoku Univ. | [Invited Talk]
Back-Bias Control technique for Suppression of Die-to-Die Delay Variability of SOTB MOS Circuits at Ultralow-Voltage (0.4 V) Operation Hideki Makiyama, Yoshiki Yamamoto, Hidekazu Oda, Shiro Kamohara, Nobuyuki Sugii, Yasuo Yamaguchi (LEAP), Koichiro Ishibashi (Univ. of Electro-Communications), Tomoko Mizutani, Toshiro Hiramoto (Univ. of Tokyo) SDM2014-94 |
Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation volta... [more] | SDM2014-94 pp.61-68 |
| ICD, SDM | 2014-08-04 09:00 |
Hokkaido | Hokkaido Univ., Multimedia Education Bldg. | [Invited Talk]
A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA Sleep Current using Reverse-Body-Bias Assisted 65nm SOTB CMOS Technology Koichiro Ishibashi (UEC), Nobuyuki Sugii (LEAP), Kimiyoshi Usami (SIT), Hideharu Amano (KU), Kazutoshi Kobayashi (KIT), Cong-Kha Pham (UEC), Hideki Makiyama, Yoshiki Yamamoto, Hirofumi Shinohara, Toshiaki Iwamatsu, Yasuo Yamaguchi, Hidekazu Oda, Takumi Hasegawa, Shinobu Okanishi, Hiroshi Yanagita (LEAP) SDM2014-62 ICD2014-31 |
[more] | SDM2014-62 ICD2014-31 pp.1-4 |
| SDM | 2014-01-29 14:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Suppression of Die-to-Die Delay Variability of Silicon on Thin Buried Oxide (SOTB) CMOS Circuits by Balanced P/N Drivability Control with Back-Bias for Ultralow-Voltage (0.4 V) Operation Hideki Makiyama, Yoshiki Yamamoto, Hirofumi Shinohara, Toshiaki Iwamatsu, Hidekazu Oda, Nobuyuki Sugii (LEAP), Koichiro Ishibashi (Univ. of Electro- Comm.), Tomoko Mizutani, Toshiro Hiramoto (Univ. of Tokyo), Yasuo Yamaguchi (LEAP) SDM2013-143 |
Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation volta... [more] | SDM2013-143 pp.35-38 |
| MW (Workshop) |
2013-12-02 - 2013-12-04 |
Overseas | King Mongkut's University of Technology North Bangkok, Thailand | An ultra-low power LNA design using SOTB CMOS devices Hoang Minh Thien, Koichiro Ishibashi (UEC) |
The paper presents a 920MHz Ultra-low power low noise amplifier (LNA) circuit, the first LNA is designed based on the 65... [more] | |
| ICD, SDM | 2012-08-03 13:10 |
Hokkaido | Sapporo Center for Gender Equality, Sapporo, Hokkaido | A Fast-Transient-Response Digital Low-Dropout Regulator Comprising Thin-Oxide MOS Transistors in 40-nm CMOS process Masafumi Onouchi, Kazuo Otsuga, Yasuto Igarashi, Toyohito Ikeya, Sadayuki Morita (Renesas Electronics), Koichiro Ishibashi (Univ. of Electro-Comm.), Kazumasa Yanagisawa (Renesas Electronics) SDM2012-82 ICD2012-50 |
A digital low-dropout (LDO) regulator comprising only thin-oxide MOS transistors was developed. The input voltage to the... [more] | SDM2012-82 ICD2012-50 pp.105-110 |
| ICD, IPSJ-ARC | 2012-01-19 11:40 |
Tokyo | [Invited Talk]
Low Power Technologies and Scaling Law Toward Future Koichiro Ishibashi (UEC-Tokyo) ICD2011-136 |
LSI density has been increasing by Moore's law, and performance of LSI has also been increasing with decreasing power di... [more] | ICD2011-136 pp.21-22 |
|
| ICD, ITE-IST | 2011-07-22 09:50 |
Hiroshima | Hiroshima Institute of Technology | On-Chip Resonant Supply Noise Reduction Using Active Decoupling Capacitors Jinmyoung Kim (Tokyo Univ.), Toru Nakura (VDEC), Hidehiro Takata, Koichiro Ishibashi (Renesas Electronics), Makoto Ikeda, Kunihiro Asada (VDEC) ICD2011-27 |
[more] | ICD2011-27 pp.69-72 |
| ICD, SDM | 2010-08-26 09:10 |
Hokkaido | Sapporo Center for Gender Equality | On-Chip Supply Resonance Noise Reduction Method for Multi-IP Cores utilizing Parasitic Capacitance of Sleep Blocks Jinmyoung Kim, Toru Nakura (Univ. of Tokyo.), Hidehiro Takata, Koichiro Ishibashi (Renesas Electronics), Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo.) SDM2010-124 ICD2010-39 |
This paper proposes an on-chip supply resonance noise reduction method for multi-IP cores utilizing parasitic capacitanc... [more] | SDM2010-124 ICD2010-39 pp.1-4 |
| VLD, IPSJ-SLDM | 2010-05-20 13:05 |
Fukuoka | Kitakyushu International Conference Center | A Wide-Range Clock Synchronizer with Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS Control Masafumi Onouchi, Yusuke Kanno, Makoto Saen, Shigenobu Komatsu (Hitachi), Yoshihiko Yasu, Koichiro Ishibashi (Renesas) VLD2010-7 |
A ``wide-range voltage-and-frequency clock synchronizer'' for maintaining synchronization during voltage-scaling transit... [more] | VLD2010-7 pp.67-72 |
| ICD, SDM | 2007-08-23 15:25 |
Hokkaido | Kitami Institute of Technology | A 1.92us-wake-up time thick-gate-oxide power switch technique for ultra low-power single-chip mobile processors Kazuki Fukuoka, Osamu Ozawa, Ryo Mori, Yasuto Igarashi, Toshio Sasaki, Takashi Kuraishi, Yoshihiko Yasu, Koichiro Ishibashi (Renesas Technology) SDM2007-153 ICD2007-81 |
A technique for controlling rush current and wake-up time of thick-gate-oxide power switches is described. Suppressing t... [more] | SDM2007-153 ICD2007-81 pp.69-73 |
| ICD | 2007-04-13 09:40 |
Oita | [Invited Talk]
A 65 nm Embedded SRAM with Wafer Level Burn-In Mode, Leak-Bit Redundancy and E-trim Fuse for Known Good Die Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono (Renesas Technology), Yuji Oda (Shikino High-Tech), Susumu Imaoka (Renesas Design), Keiichi Usui (Daioh Electric), Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) ICD2007-11 |
We propose a Wafer Level Burn-In (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair s... [more] | ICD2007-11 pp.59-64 |
|
| ICD, ITE-CE | 2006-12-15 11:15 |
Hiroshima | Low Power SOC Design using Partial-Trench-Isolation ABC SOI for sub-100-nm LSTP technology Osamu Ozawa, Kazuki Fukuoka, Yasuto Igarashi, Takashi Kuraishi, Yoshihiko Yasu, Yukio Maki, Takashi Ipposhi, Toshihiko Ochiai, Masayoshi Shirahata, Koichiro Ishibashi (Renesas) |
[more] | ICD2006-163 pp.115-119 |
|
| ICD, SDM | 2006-08-18 12:05 |
Hokkaido | Hokkaido University | A 65 nm Ultra-High-Density Dual-port SRAM with 0.71um2 8T-cell for SoC Susumu Imaoka (Renesas Design), Koji Nii (Renesas Technology), Yasuhiro Masuda (Renesas Design), Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Motoshige Igarashi, Kazuo Tomita, Nobuo Tsuboi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) |
We propose a new access scheme of synchronous dual-port (DP) SRAM that minimizes area of 8T-DP-cell and keeps cell stabi... [more] | SDM2006-148 ICD2006-102 pp.133-136 |
| ICD, SDM | 2006-08-18 14:35 |
Hokkaido | Hokkaido University | A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits Makoto Yabuuchi, Shigeki Ohbayashi, Koji Nii, Yasumasa Tsukamoto (Renesas Technology), Susumu Imaoka (Renesas Design), Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Hiroshi Makino, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) |
[more] | SDM2006-151 ICD2006-105 pp.149-153 |
| ICD | 2006-04-14 13:50 |
Oita | Oita University | Worst-Case Ananlysis to Obtain Stable Read/Write DC Margin of High Density 6T-SRAM-Array with Local Vth Variability Yasumasa Tsukamoto, Koji Nii (Renesas Technology), Susumu Imaoka (Renesas Design), Yuji Oda (Shikino High-Tech.), Shigeki Ohbayashi, Makoto Yabuuchi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) |
[more] | ICD2006-18 pp.97-102 |
| SIP, ICD, IE, IPSJ-SLDM | 2005-10-21 09:20 |
Miyagi | Ichinobo, Sakunami-Spa | Substrate Noise Reduction and Random Variability Neutralization with Self Adjusted Forward Body Bias Control Yoshihide Komatsu, Koichiro Ishibashi, Toshiro Tsukada, Masaharu Yamamoto (STARC), Kenji Shimazaki, Mitsuya Fukazawa, Makoto Nagata (Kobe Univ.) |
[more] | SIP2005-116 ICD2005-135 IE2005-80 pp.7-12 |
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