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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 7 of 7  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2013-12-13
13:50		 Ishikawa   Construction of High Quality Delay Test Set Using Fast On-Chip Delay Measurement
Kentaroh Katoh (TNCT), Haruo Kobayashi (Gunma University) DC2013-70		 Today, low power and high speed LSIs such as microprocessors and SoCs are indispensable in various consumer devices and ... [more] DC2013-70
pp.13-16
DC 2013-06-21
16:00		 Tokyo Kikai-Shinko-Kaikan Bldg. An Online Interconnect Test of SoC with Boundary Scan Shift and Embedded Reconfigurable Core
Kentaroh Katoh (TNCT) DC2013-14		 This paper presents an online Interconnect test of SoC with Boundary Scan Shift and embedded reconfigurable core. The pr... [more] DC2013-14
pp.25-29
DC, CPSY 2013-04-26
16:40		 Tokyo   On-Chip Delay Measurement Using Adjacent Test Architecture
Kentaroh Katoh (TNCT) CPSY2013-8 DC2013-8		 This paper proposes an on-chip delay measurement using adjacent test architecture with TDC (Time to Digital Converter). ... [more] CPSY2013-8 DC2013-8
pp.43-48
DC 2012-06-22
13:25		 Tokyo Room B3-1 Kikai-Shinko-Kaikan Bldg A Reduction Technique of Input Sequences for Time-Multiplexed On-Chip Path Delay Measurement Using Embedded Delay Measurement Circuit
Kentaroh Katoh (TNCT) DC2012-10		 Time-multiplexed delay measurement is useful for the reduction of the measurement time of the on-chip delay measurement... [more] DC2012-10
pp.7-13
DC 2010-02-15
13:20		 Tokyo Kikai-Shinko-Kaikan Bldg. Reduction of execution times and areas for delay measurement by subtraction
Toru Tanabe, Hirohisa Minato, Kentaroh Katoh, Kazuteru Namba, Hideo Ito (Chiba Univ.) DC2009-71		 Since VLSI is in nanoscase size, high density and high speed in recent years, small-delay defects which change propagati... [more] DC2009-71
pp.39-44
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]		 2007-11-20
10:05		 Fukuoka Kitakyushu International Conference Center 2-Step Test Data Compression using Scan FF with Two Pattern Testability
Kentaroh Katoh, Kazuteru Namba, Hideo Ito (Chiba Univ.) VLD2007-70 DC2007-25		 This paper presents a stuck-at test data compression technique using the scan flip flops with delay fault testability. T... [more] VLD2007-70 DC2007-25
pp.1-6
CPSY, DC 2006-04-14
10:40		 Tokyo Takeda Hall Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices
Kentaroh Katoh, Yumin Yao, Kazuteru Namba, Hideo Ito (チバダイ) 		This paper proposes a BIST (Built-In Self Test) method for testing the PEs (Processing Elements) of multi-context based ... [more] CPSY2006-4 DC2006-4
pp.19-24
 Results 1 - 7 of 7  /   
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