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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, ICD 2008-03-07
16:10		 Okinawa TiRuRu New technology of independent-gate controlled Double-Gate transistor for system LSI
Yu Hiroshima, Keisuke Okamoto, Keisuke Koizumi, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-168 ICD2007-191		 New design technology of independent-gate controlled Double-Gate transistor realized high density design more than FinFE... [more] VLD2007-168 ICD2007-191
pp.69-74
VLD, ICD 2008-03-07
16:35		 Okinawa TiRuRu New design technology of independent-Gate controlled Stacked type 3D transistor for system LSI
Yu Hiroshima, Keisuke Okamoto, Keisuke Koizumi, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-169 ICD2007-192		 New design technology of Independent-Gate controlled Stacked type 3D transistor has feature of Independent-gate controll... [more] VLD2007-169 ICD2007-192
pp.75-80
VLD, ICD 2008-03-07
17:00		 Okinawa TiRuRu Design of High Density LSI with Three-Dimensional Transistor FinFET -- Effect of pattern Area Reduction with CMOS Cell Library --
Keisuke Okamoto, Keisuke Koizumi, Yu Hiroshima, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-170 ICD2007-193		 (To be available after the conference date) [more] VLD2007-170 ICD2007-193
pp.81-86
ICD, SDM 2007-08-24
13:50		 Hokkaido Kitami Institute of Technology Design of High Density LSI with Three-Dimensional Transistor FinFET -- Effect of Pattern Area Reduction with CMOS Cell Library --
Keisuke Okamoto, Keisuke Koizumi, Yu Hiroshima, Shigeyoshi Watanabe (SIT) SDM2007-163 ICD2007-91		 New design method of system LSI with FinFET has been developed. Using planar+FinFET architecture the pattern area of CMO... [more] SDM2007-163 ICD2007-91
pp.119-124
ICD, SDM 2007-08-24
14:15		 Hokkaido Kitami Institute of Technology Ｄesign Method of system LSI with FinFET type DTMOS
Yu Hiroshima, Shigeyoshi Watanabe, Keisuke Okamoto, Keisuke Koizumi (SIT) SDM2007-164 ICD2007-92		 Planar DTMOS has a problem of increase of pattern area. Using FinFET type DTMOS excess pattern area of connect to gate a... [more] SDM2007-164 ICD2007-92
pp.125-130
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