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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF | 2015-06-19 15:10 |
Kyoto | Kyoto University | Consideration of the one-dimensional array processor suitable for a shock tube problem by FPGA Keisuke Hirofuji, Ryo Okuda, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ)  RECONF2015-9 |
[more] | RECONF2015-9 pp.47-52 |
| RECONF | 2015-06-20 15:25 |
Kyoto | Kyoto University | Consideration of a reconfigurable device MPLD constructed with MLUTs that equips a crossbar switch Naoya Tokusada, Tetsuo Hironaka, Kazuya Tanigawa (HCU), Takashi Ishiguro (Taiyo Yuden) RECONF2015-25 |
[more] | RECONF2015-25 pp.135-140 |
| CPSY | 2014-11-14 11:45 |
Hiroshima | Hiroshima University | An implementation of high-throughput computing system using the GPU Kazuya Tani, Koji Nakano, Yasuaki Ito (Hiroshima Univ.) CPSY2014-70 |
[more] | CPSY2014-70 pp.93-98 |
| RECONF | 2014-09-19 13:05 |
Hiroshima | Discussion for speed up of three-dimensional space imaging using sound waves Keiko Oda, Akira Kojima, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) RECONF2014-30 |
In general, the most of methods for three-dimensional imaging using sound waves measure the distance of objects by analy... [more] | RECONF2014-30 pp.75-80 |
|
| RECONF | 2014-09-19 13:30 |
Hiroshima | FPGA implementation of a Compact Processor Yukiyama for tiny SoC Yuichi Watanabe, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) RECONF2014-31 |
This paper proposes a small soft-core processor architecture that can be mapped to a CPLD. This paper describes the det... [more] |
RECONF2014-31 pp.81-86 |
|
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 11:40 |
Kanagawa | Hiyoshi Campus, Keio University | Study of accelerator connection using the peripheral bus of OpenMSP430 Ayano Fukuju, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) VLD2013-125 CPSY2013-96 RECONF2013-79 |
This paper reports evaluating relationship between several transfer methods and application processing time for the syst... [more] | VLD2013-125 CPSY2013-96 RECONF2013-79 pp.137-142 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 08:30 |
Kagoshima | Soft-core microprocessor for small reconfigurable device Yuichi Watanabe, Taisuke Yamamoto, Yuki Yoshida, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) RECONF2013-46 |
This paper proposes a soft-core processor implemented by using hardware description language that is possible to be imp... [more] |
RECONF2013-46 pp.39-44 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 14:35 |
Kagoshima | Architecture Evaluation Using The Place-and-Route Tool of a Reconstruction Device MPLD Tomoya Yamashita, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Takashi Ishiguro (TAIYO YUDEN) RECONF2013-55 |
In this paper, we evaluate some logic and interconnection structures for MPLD, which is a basic architecture for reconf... [more] |
RECONF2013-55 pp.87-92 |
|
| RECONF | 2013-09-18 17:25 |
Ishikawa | Japan Advanced Institute of Science and Technology | Nonvolatile reconfigurable device development platform using a phase change material Takumi Michida, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.), Kenichi Shimomai, Takashi Ishiguro (TAIYO YUDEN) RECONF2013-25 |
We have studied a development technique of nonvolatile reconfigurable device MPLD using the phase change memory. The de... [more] |
RECONF2013-25 pp.31-36 |
| RECONF | 2013-09-19 09:50 |
Ishikawa | Japan Advanced Institute of Science and Technology | Investigation of the area reduction by pass transistor logic in reconfigurable device MPLD Yuki Yoshida, Takumi Michida, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.), Kenichi Shimomai, Takashi Ishiguro (TAIYO YUDEN) RECONF2013-28 |
Reconfigurable device Memory-based Programmable Logic Device (MPLD) consists of an array of Multiple Look Up Table (MLUT... [more] | RECONF2013-28 pp.49-54 |
| RECONF | 2013-05-20 16:50 |
Kochi | Kochi Prefectural Culture Hall | Proposal of a Dependable Fine-grained Reconfigurable Device with ECC Technology Yuki Yoshida, Kentaro Takaki, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.), Kenichi Shimomai, Takashi Ishiguro (TAIYO YUDEN) RECONF2013-6 |
Soft errors by cosmic rays and noise in a Field Programmable Gate Array (FPGA) are getting a big problem since the semic... [more] | RECONF2013-6 pp.31-36 |
| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-16 09:10 |
Kanagawa | Architecture Evaluation of a Reconfigurable Device MPLD Tomoya Yamashita, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Takashi Ishiguro (TAIYO YUDEN) VLD2012-107 CPSY2012-56 RECONF2012-61 |
In this paper, we discuss the detailed structure of MPLD, an architecture for realizing reconfigurable devices. MPLD co... [more] |
VLD2012-107 CPSY2012-56 RECONF2012-61 pp.1-6 |
|
| RECONF | 2012-05-29 14:00 |
Okinawa | Tiruru (Naha Okinawa, Japan) | Implementation of Square Root Calculator on Reconfigurable Processor DS-HIE Takashi Ueda, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) RECONF2012-9 |
[more] | RECONF2012-9 pp.49-54 |
| VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2012-01-26 15:25 |
Kanagawa | Hiyoshi Campus, Keio University | Evaluation of Improvement Techniques for Placement and Routing on MPLD : a New Reconfigurable Device Ken Taomoto, Masato Inagi, Hideyuki Kawabata, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Masayuki Sato, Takashi Ishiguro (Taiyo Yuden), Toshiaki Kitamura, Masatoshi Nakamura (Hiroshima City Univ) |
(To be available after the conference date) [more] | |
| RECONF | 2011-09-26 11:10 |
Aichi | Nagoya Univ. | Feasibility study of nonvolatile reconfiguralbe device by using a standard CMOS logic process Shuji Kunimitsu, Mamoru Terauchi, Kazuya Tanigawa, Tetsuo Hironaka (HCU), Masayuki Sato, Takashi Ishiguro (TAIYO YUDEN) RECONF2011-23 |
In this paper, we consider the realization of nonvolatile PLD, based on the new recon gurable device architecture MPLD.... [more] |
RECONF2011-23 pp.7-12 |
| RECONF | 2011-09-27 11:00 |
Aichi | Nagoya Univ. | Performance Evaluation of Power Monitoring Programs on Reconfigurable Processor DS-HIE Kyohei Tao, Takatoshi Tamaoki, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) RECONF2011-36 |
In recently years, a smart grid has been emerging as a new power network. As the smart grid needs a smart meter, a sma... [more] |
RECONF2011-36 pp.81-86 |
| LQE, OPE, OCS | 2010-10-29 09:20 |
Fukuoka | Mojiko Retro Town, Minato house | Calculation of Nonreciprocal Phase Shift in Magneto-Optic Waveguides with (CeY)3Fe5O12 Layer Kazutaka Isoda, Kazuya Tani, Shun Igarashi, Yuki Uchiumi, Hideki Yokoi (Shibaura Inst. of Tech.) OCS2010-72 OPE2010-108 LQE2010-81 |
[more] | OCS2010-72 OPE2010-108 LQE2010-81 pp.103-106 |
| RECONF | 2010-09-16 13:50 |
Shizuoka | Shizuoka University (Faculty of Eng., Hall 2) | A Consideration of Reconfigurable Processor for RSA Cryptography Takatoshi Tamaoki, Kazuya Tanigawa, Tetsuo Hironaka (hcu) RECONF2010-22 |
Encrypting and decrypting RSA require many exponentiation calculations, and modulo calculation with bit-with wider than... [more] |
RECONF2010-22 pp.25-30 |
| RECONF | 2010-09-16 15:25 |
Shizuoka | Shizuoka University (Faculty of Eng., Hall 2) | Evaluation of Multiple-Precision Floating-Point Accelerator HP-DSFP through Applications. Yuki Yoshioka, Tomoyuki Kawamoto, Taiga Ban, Kazuya Tanigawa, Tetsuo Hironaka (HCU) RECONF2010-25 |
In recent years, many kinds of scientific application programs, such as Fluid analysis, Feynman loop integrals and conju... [more] | RECONF2010-25 pp.43-48 |
| RECONF | 2010-09-16 16:10 |
Shizuoka | Shizuoka University (Faculty of Eng., Hall 2) | An SA-based Placement and Routing Method Considering Cell Congestion for MPLDs Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Masayuki Sato, Takashi Ishiguro (TAIYO YUDEN) RECONF2010-26 |
[more] | RECONF2010-26 pp.49-54 |
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