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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, ICD | 2008-03-07 14:40 |
Okinawa | TiRuRu | Implementation and Evaluation of Network Security using An Embedded Programmable Logic Matrix (ePLX) Mitsutaka Matsumoto, Shun Kimura (Ritsumeikan Univ.), Hirofumi Nakano, Takenobu Iwao, Yoshihiro Okuno, Kazutami Arimoto (Renesas Technology Corp.), Tomonori Izumi, Takeshi Fujino (Ritsumeikan Univ.)  VLD2007-165 ICD2007-188 |
Low Cost Network Appliance with low power microprocessor must be connected with networks in order to realize ubiquitous ... [more] | VLD2007-165 ICD2007-188 pp.53-58 |
| ICD, ITE-CE | 2007-12-14 14:40 |
Kochi | A multi matrix-processor core architecture for real-time image processing SoC Katsuya Mizumoto, Takayuki Gyohten, Tetsushi Tanizaki, Soichi Kobayashi, Masami Nakajima, Hiroyuki Yamasaki, Hideyuki Noda, Motoki Higashida, Yoshihiro Okuno, Kazutami Arimoto (Renesas) ICD2007-138 |
This paper describes a real time image processing SoC(MX-SoC) with programmable multi matrix -processor(MX-Core) archite... [more] | ICD2007-138 pp.107-111 |
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| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 15:10 |
Fukuoka | Kitakyushu International Conference Center | A Development of the Auto mapping tool for embedded Programmable Logic matriX (ePLX) and the study of ePLX local architecture Kouta Ishibashi, Yoshiyuki Tanaka, Mitsutaka Matsumoto (Ritsumeikan Univ.), Hirofumi Nakano, Takenobu Iwao, Yoshihiro Okuno, Kazutami Arimoto (Renesas Technology), Masaya Yoshikawa (Meijo Univ.), Tomonori Izumi, Takeshi Fujino (Ritsumeikan Univ.) RECONF2007-32 |
We propose a ePLX(embedded Programmable Logic matriX)which will be embedded in SoC.The ePLX consists of small area and a... [more] | RECONF2007-32 pp.1-6 |
| CPSY | 2007-10-25 13:00 |
Kumamoto | Kumamoto University | The application of the massively parallel processor based on the matrix architecture Katsuya Mizumoto, Hiroyuki Yamasaki, Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten, Masami Nakajima, Motoki Higashida, Yoshihiro Okuno, Kazutami Arimoto (Renesas) CPSY2007-24 |
We have developed programmable matrix-processor "MX-1". The MX-1 consists of MX-Core and a control CPU. The MX-Core is a... [more] | CPSY2007-24 pp.1-5 |
| CPSY | 2007-10-25 13:40 |
Kumamoto | Kumamoto University | The program development method of the massively parallel processor based on the matrix architecture. Hiroyuki Yamasaki, Katsuya Mizumoto, Hideyuki Noda, Tetsu Nishijima, Kanako Yoshida, Takeaki Sugimura, Takashi Kurafuji, Osamu Yamamoto, Yoshihiro Okuno, Kazutami Arimoto (Renesas) CPSY2007-25 |
Recently, the installed applications in the digital devices has been remarkably progressed. Considering these background... [more] | CPSY2007-25 pp.7-12 |
| CPSY | 2007-10-25 15:10 |
Kumamoto | Kumamoto University | Acceleration of Multimedia Data Processing with CAM-Enhanced Massive-Parallel SIMD Matrix Processor Takeshi Kumaki, Masakatsu Ishizaki, Masaharu Tagami, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.), Takayuki Gyohten, Hideyuki Noda, Yasuto Kuroda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito (Renesas Technology) CPSY2007-27 |
A multimedia processor requires four capabilities, fast processing, small area size, low power consumption and programma... [more] | CPSY2007-27 pp.19-24 |
| CPSY | 2007-10-25 15:50 |
Kumamoto | Kumamoto University | Acceleration of AES Encryption with CAM-Enhanced Massive-Parallel SIMD Matrix Processor Masakatsu Ishizaki, Takeshi Kumaki, Masaharu Tagami, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.), Takayuki Gyohten, Hideyuki Noda, Yoshihiro Okuno, Kazutami Arimoto (Renesas Technology) CPSY2007-28 |
We have previously reported that the Content Addressable Memory (CAM)-enhanced massive-parallel Single Instruction Multi... [more] | CPSY2007-28 pp.25-30 |
| RECONF | 2007-05-17 17:20 |
Ishikawa | Kanazawa Bunka Hall | A Discussion on a Router for embedded Programmable Logic matriX (ePLX) Naoki Okuno, Tomonori Izumi, Takeshi Fujino (Ritsumeikan Univ.), Takenobu Iwao, Hirofumi Nakano, Yoshihiro Okuno, Kazutami Arimoto (Renesas) RECONF2007-9 |
We propose a fine-grained programmable logic architecture designed to be embedded in system-on-chips (SoCs) to enhance t... [more] | RECONF2007-9 pp.49-54 |
| ICD | 2007-04-12 14:20 |
Oita | A voltage scalable advanced DFM RAM with accelerated screening for low power SoC platform Hiroki Shimano, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto (Renesas Technology Corp.) ICD2007-8 |
The advanced-DFM (Design For Manufacturability) RAM provides the solution for the limitation of SRAM voltage scaling dow... [more] | ICD2007-8 pp.41-46 |
|
| ICD | 2007-04-13 11:00 |
Oita | [Invited Talk]
A high density embedded memory for Soc: Twin transistor RAM(TT-RAM) Kazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Katsumi Dosaka (Renesas) ICD2007-13 |
A high speed/low power dissipation high density Twin transistor RAM(TT-RAM) has been developed as SOI CMOS platform memo... [more] | ICD2007-13 pp.71-76 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2007-01-18 13:25 |
Tokyo | Keio Univ. Hiyoshi Campus | Analysis of design architecture of ePLX ( embedded Programmable Logic matriX) and Evaluation of circuit mapping Tomoo Hishida, Kouta Ishibashi, Shun Kimura, Naoki Okuno, Mitsutaka Matsumoto (Ritsumeikan Univ.), Hirofumi Nakano, Takenobu Iwao, Yoshihiro Okuno, Kazutami Arimoto (Renesas Technology), Tomonori Izumi, Takeshi Fujino (Ritsumeikan Univ.) |
Recently, non-recurring engineering costs (NREs), including cost of mask-sets, and engineering design efforts are critic... [more] | VLD2006-100 CPSY2006-71 RECONF2006-71 pp.37-42 |
| ICD, ITE-CE | 2006-12-15 12:05 |
Hiroshima | Multiple CAM Matches and Self-adapting Codeword Table for Optimized Real-time Huffman Encoding Masakatsu Ishizaki, Takeshi Kumaki, Yutaka Kono, Masaharu Tagami, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.), Yasuto Kuroda, Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito (Renesas Technology Corp.) |
[more] | ICD2006-165 pp.125-130 |
|
| ICD, SIP, IE, IPSJ-SLDM | 2006-10-26 11:30 |
Miyagi | Super parallel SIMD processor with CAM based high-speed pattern matching capability Yutaka Kono, Takeshi Kumaki, Masakatsu Ishizaki, Masaharu Tagami, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.), Takayuki Gyohten, Hideyuki Noda, Yasuto Kuroda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito (Renesas) |
A super parallel SIMD processor has been developed for handling the increasing amount of multimedia data efficiently. ... [more] |
SIP2006-90 ICD2006-116 IE2006-68 pp.39-44 |
|
| ICD | 2006-04-13 14:50 |
Oita | Oita University | [Special Invited Talk]
New Memory Device on SoC Platform Kazutami Arimoto (Renesas) |
Advanced SoC platform which is based on open architecture consists of hardware/ software interconnection and scalable c... [more] | ICD2006-7 pp.37-42 |
| ICD, VLD | 2006-03-10 15:35 |
Okinawa | An On-chip PVT Control System for Worst-caseless Lower Voltage SoC Design Takayuki Gyohten, Fukashi Morishita (Renesas Technology Corp.), Mako Okamoto (Daioh Electric Corp.), Katsumi Dosaka, Kazutami Arimoto (Renesas Technology Corp.) |
In this paper, we propose on-chip PVT (process, voltage, and temperature) control system for worst-caseless lower voltag... [more] | VLD2005-132 ICD2005-249 pp.61-66 |
|
| SIP, ICD, IE, IPSJ-SLDM | 2005-10-20 16:10 |
Miyagi | Ichinobo, Sakunami-Spa | A Soft-Error-Immune TCAM Archiecture with Associated Embedded DRAM Yuji Yano, Hideyuki Noda, Katsumi Dosaka, Fukashi Morishita, Kazunari Inoue, Toshiyuki Ogawa, Kazutami Arimoto (Renesas) |
[more] | SIP2005-112 ICD2005-131 IE2005-76 pp.101-105 |
| SIP, ICD, IE, IPSJ-SLDM | 2005-10-20 16:30 |
Miyagi | Ichinobo, Sakunami-Spa | A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI Takayuki Gyohten, Fukashi Morishita, Hideyuki Noda (Renesas Technology Corp.), Mako Okamoto (Daioh Electric Corp.), Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto (Renesas Technology Corp.) |
We propose a novel capacitorless twin-transistor random access memory (TTRAM). The 2Mb test device has been fabricated o... [more] | SIP2005-113 ICD2005-132 IE2005-77 pp.107-112 |
| ICD, SDM | 2005-08-18 16:20 |
Hokkaido | HAKODATE KOKUSAI HOTEL | SOI; the Trump Card of SOCs in Sub. 50-nm Era
-- Techniques that SOI Conquers Bulk! -- Tadayoshi Enomoto (Chuo Univ.), Takakuni Douseki (NTT), Kazutami Arimoto (Renesas), Jiroh Ida (Oki), Takashi Ipposhi (Renesas), Kazuhiko Miki (Toshiba), Masanao Yamaoka (Hitachi), Makoto Yoshimi (SOITEC) |
(Advance abstract in Japanese is available) [more] | SDM2005-142 ICD2005-81 pp.85-90 |
| RECONF | 2005-05-13 13:00 |
Kyoto | Kyoto University | [Invited Talk]
Programmable Device Technologies for SoC Embedded Applications Masami Nakajima, Hideyuki Noda, Kazutami Arimoto (Renesas) |
SoC for digital consumer market requires short time and low cost of development and easy system change. SoC development ... [more] | RECONF2005-21 pp.37-42 |
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