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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 12:45 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | 2-step Charge Pump Voltage Booster Circuit for Micro Energy Harvesting Tomoya Kimura, Hiroyuki ochi (Ritsumeikan Univ.)  VLD2016-46 DC2016-40 |
This report proposes L1L5-type 2-step charge pump circuit that is suitable for boosting efficiently the subthreshold inp... [more] | VLD2016-46 DC2016-40 pp.13-18 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 10:30 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Area-efficient LUT-like Programmable Logic Using Atom Switch and its Delay-optimal Mapping Algorithm Toshiki Higashi, Hiroyuki Ochi (Ritsumeikan Univ.) RECONF2016-45 |
This paper proposes a delay model for 0-1-$A$-$overline{A}$ LUT and a delay-optimal mapping algorithm for it. 0-1-$A$-$o... [more] | RECONF2016-45 pp.29-34 |
| DC, CPSY | 2015-04-17 13:25 |
Tokyo | A study of processor architecture suited for intelligent sensing system Hiroki Hihara, Akira Iwasaki (Univ. of Tokyo), Masanori Hashimoto (Osaka Univ./JST CREST), Hiroyuki Ochi (Rits/JST CREST), Yukio Mitsuyama (KUT/JST CREST), Hidetoshi Onodera (Kyoto Univ./JST CREST), Hiroyuki Kanbara (ASTEM/JST CREST), Kazutoshi Wakabayashi, Takashi Takenaka, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada (NEC/JST CREST) CPSY2015-8 DC2015-8 |
Sensor nodes are now important elements for the system of social infrastructure, and thus intelligent processing capabil... [more] | CPSY2015-8 DC2015-8 pp.43-48 |
|
| ICD, ITE-IST | 2013-07-05 17:40 |
Hokkaido | San Refre Hakodate | Failure mode analysis for flip-flops at low voltages Takafumi Fujita, Junya Kawashima, Masayuki Hiromoto (Kyouto Univ.), Hiroshi Tsutsui (Hokkaido Univ.), Hiroyuki Ochi (Ritsumeikan Univ.), Takashi Sato (Kyouto Univ.) ICD2013-45 |
Towards the reducing power consumption, subthreshold circuit which operates at a low voltage below the threshold voltage... [more] | ICD2013-45 pp.129-134 |
| RECONF | 2013-05-20 17:40 |
Kochi | Kochi Prefectural Culture Hall | Flexible reliability mixed-grained reconfigurable architecture supporting behavioral synthesis Hiroaki Konoura, Dawood Alnajjar (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. Tech.), Hiroyuki Ochi (Ritsumeikan Univ.), Takashi Imagawa (Kyoto Univ.), Shinichi Noda, Kazutoshi Wakabayashi (NEC), Masanori Hashimoto, Takao Onoye (Osaka Univ.) RECONF2013-8 |
This paper proposes a mixed-grained reconfigurable architecture that supports C-based behavioral synthesis and flexibl... [more] |
RECONF2013-8 pp.41-46 |
| ICD | 2012-12-17 10:20 |
Tokyo | Tokyo Tech Front | Verification of an Estimation Method of Minimum Operation Voltage by Measurement Junya Kawashima, Hiroyuki Ochi, Hiroshi Tsutsui, Takashi Sato (Kyoto Univ.) ICD2012-87 |
[more] | ICD2012-87 pp.3-8 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 13:00 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Accurate I/O Buffer Impedance Self-adjustment using Threshold Voltage and Temperature Sensors Zhi Li, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato (Kyoto Univ.) VLD2012-79 DC2012-45 |
With the increased operating frequency and the reduction of feature size, achieving low error-rate data transmission be... [more] |
VLD2012-79 DC2012-45 pp.117-122 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-28 15:10 |
Miyazaki | NewWelCity Miyazaki | An Acceleration Method for Power Grid Analysis using Block-Iterative Algorithm Takumi Morishita, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato (Kyoto Univ.) VLD2011-63 DC2011-39 |
Because of its extremely large size, power grid analysis has been a computationally challenging problem both in terms of... [more] | VLD2011-63 DC2011-39 pp.67-71 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-28 15:40 |
Miyazaki | NewWelCity Miyazaki | A Fast Transient Analysis of Linear Circuit using Quasi Zero Variance Importance Sampling Tetsuro Miyakawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato (Kyoto Univ.) VLD2011-64 DC2011-40 |
We propose a method to accelerate random walk based transient analysis of linear circuits. Our method uses quasi-zero-v... [more] | VLD2011-64 DC2011-40 pp.73-78 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-28 16:30 |
Miyazaki | NewWelCity Miyazaki | A study on parameter estimation for modeling of random-telegraph noise Hiromitsu Awano, Hirofumi Shimizu, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato (Kyoto Univ.) VLD2011-66 DC2011-42 |
Random Telegraph Noise (RTN) is a physical phenomenon that is considered to determine reliability and performance of cir... [more] | VLD2011-66 DC2011-42 pp.85-90 |
| VLD | 2010-09-28 14:35 |
Kyoto | Kyoto Institute of Technology | A study of temperature characteristics of ring-oscillator based threshold voltage estimation Takumi Uezono, Hiroyuki Ochi, Takashi Sato (Kyoto Univ.) VLD2010-53 |
Yield and reliability improvement is one of the most serious concerns for nanometer-technology chip designs. Recenly, s... [more] | VLD2010-53 pp.67-70 |
| VLD, IPSJ-SLDM | 2010-05-19 17:00 |
Fukuoka | Kitakyushu International Conference Center | Error Propagation Probability-based Selective TMR for Reliable Coarse-Grained Reconfigurable Architecture Hiroshi Yuasa, Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato (Kyoto Univ.) VLD2010-4 |
Advancing CMOS process technology implies decreasing operating voltages, leaving LSI increasingly vulnerable to temporar... [more] | VLD2010-4 pp.37-42 |
| ICD | 2010-04-23 16:05 |
Kanagawa | Shonan Institute of Tech. | [依頼講演]Digital Rosetta Stone: A Sealed Permanent Memory with Inductive-Coupling Power and Data Link Yuxiang Yuan, Noriyuki Miura (Keio Univ.), Shigeki Imai (Sharp), Hiroyuki Ochi (Kyoto Univ.), Tadahiro Kuroda (Keio Univ.) ICD2010-20 |
A permanent memory system is prototyped in 0.18µm CMOS. Data is stored in MROM, and stacked wafers are completely s... [more] | ICD2010-20 pp.103-105 |
| SIS | 2008-06-12 11:45 |
Hokkaido | Hardware Implementation of Run-time Learning for Object Recognition Kazunori Kimura, Hiroyuki Ochi (Kyoto Univ.), Ryusuke Miyamoto (NAIST) SIS2008-5 |
Cascade Particle Filter is one of the latest schemes which enables highly accurate object recognition. In order to app... [more] |
SIS2008-5 pp.23-28 |
|
| SIS | 2008-06-13 13:15 |
Hokkaido | An Architecture of Photo Core Transform in HD Photo Coding System for Embedded System of Various Bandwidths Koichi Hattori (Kyoto Univ.), Hiroshi Tsutsui (Osaka Univ.), Hiroyuki Ochi (Kyoto Univ.), Yukihiro Nakamura (Ritsumeikan Univ.) SIS2008-21 |
In this paper, we propose a novel architecture of photo core transform (PCT) which is used as transformation of image da... [more] | SIS2008-21 pp.39-44 |
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| DC, CPSY, IPSJ-SLDM, IPSJ-EMB | 2008-03-28 09:50 |
Kagoshima | An Asynchronous IEEE754-standard Single-precision Floating-point Divider for FPGA Masayuki Hiromoto, Hiroyuki Ochi (Kyoto Univ.), Yukihiro Nakamura (Ritsumeikan Univ.) DC2007-105 CPSY2007-101 |
Synchronous design methodology is widely used for today's digital circuits. However, it is difficult to reuse a highly-... [more] | DC2007-105 CPSY2007-101 pp.127-132 |
|
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-17 14:10 |
Kanagawa | Hiyoshi Campus, Keio University | A Tile Based Dynamically Reconfigurable Architecture with Dual ALU-array/RISC Processor Operating Mode Capability Shin'ichi Kouyama, Masayuki Hiromoto, Hiroyuki Ochi (Kyoto Univ.), Yukihiro Nakamura (Ritsumeikan Univ.) VLD2007-128 CPSY2007-71 RECONF2007-74 |
[more] | VLD2007-128 CPSY2007-71 RECONF2007-74 pp.59-64 |
| VLD, IPSJ-SLDM | 2007-05-11 10:55 |
Kyoto | Kyodai Kaikan | An Asynchronous Single-precision Floating-point Divider and its Implementation on FPGA Masayuki Hiromoto, Atsuko Takahashi, Shin'ichi Kouyama, Hiroyuki Ochi (Kyoto Univ.), Yukihiro Nakamura (Ritsumeikan Univ.) VLD2007-10 |
Synchronous design methodology is widely used for today's digital circuits. However, highly optimized synchronous design... [more] | VLD2007-10 pp.19-24 |
| RECONF | 2006-05-18 11:30 |
Miyagi | TOHOKU UNIVERSITY | A Retargetable Compiler for Cell-Array Based Self-Reconfigurable Architecture Masayuki Hiromoto, Shin'ichi Kouyama, Kentaro Nakahara, Hiroshi Tsutsui, Hiroyuki Ochi, Yukihiro Nakamura (Kyoto Univ.) |
Simulation-based quantitative performance evaluation using specific applications is indispensable for developing archite... [more] | RECONF2006-2 pp.7-12 |
| MoNA, IN (Joint) |
2005-11-17 11:10 |
Fukuoka | Fukuoka Institute of Technology | Implementation of home appliance control system using Peer-to-Peer technology Eiji Omata, Norihiro Ishikawa, Hiromitsu Sumino (NTT DoCoMo), Tomonori Izumi (Ritsumei Univ.), Hiroyuki Ochi, Yukihiro Nakamura (Kyoto Univ.) |
[more] | MoMuC2005-61 pp.19-24 |
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