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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| QIT (2nd) |
2022-12-08 14:00 |
Kanagawa | Keio Univ. (Primary: On-site, Secondary: Online) |
[Poster Presentation]
Universal quantum computation using qubit array that is controllable only in units of column and row Saki Tanaka, Tatsuya Tomaru, Chihiro Yoshimura, Hiroyuki Mizuno (HITACHI) |
two-dimensional qubit array can be highly integrated by making the control lines common in units of column and row. Sing... [more] | |
| ICD | 2015-04-17 14:55 |
Nagano | [Invited Talk]
An 1800-Times-Higher Power-Efficient 20k-spin Ising Chip for Combinatorial Optimization Problem with CMOS Annealing Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno (Hitachi)  ICD2015-13 |
A new computing architecture using Ising model that effectively solves combinatorial optimization problems is proposed, ... [more] | ICD2015-13 pp.63-68 |
|
| MW | 2010-05-14 09:55 |
Hyogo | University of Hyogo | Design Method of Lumped-Element Dual-Bnad Wilkinson Power Dividers Hiroyuki Mizuno, Tadashi Kawai, Isao Ohta, Akira Enokihara (Univ. of Hyogo) MW2010-21 |
This paper treats a design method of dual-band lumped-element Wilkinson power dividers using series and parallel LC-reso... [more] | MW2010-21 pp.39-43 |
| MSS | 2010-01-21 13:25 |
Aichi | Toyota Central R&D Labs. | Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme Masafumi Onouchi, Keisuke Toyama, Toru Nojiri, Makoto Satoh (Hitachi), Masayoshi Mase, Jun Shirako (Waseda Univ.), Mikiko Sato (Tokyo Univ. of Agr and Tech.), Masashi Takada, Masayuki Ito (Renesas), Hiroyuki Mizuno (Hitachi), Mitaro Namiki (Tokyo Univ. of Agr and Tech.), Keiji Kimura, Hironori Kasahara (Waseda Univ.) CST2009-38 |
We developed a software-execution framework for scalable increase of execution speed and low-power consumption based on ... [more] | CST2009-38 pp.7-12 |
| MW | 2009-11-20 12:10 |
Kagoshima | Tanegashima | Broadband Compact Rat-Race Circuits Using Composite Right-/Left-Handed Transmission Lines Tadashi Kawai, Hiroyuki Mizuno, Isao Ohta, Akira Enokihara (Univ. of Hyogo) MW2009-142 |
This paper treats a design method of broadband compact 180-degree hybrids using composite right-/left-handed transmissio... [more] | MW2009-142 pp.81-86 |
| MW | 2008-05-30 10:45 |
Kyoto | Kyoto Univ. | Unequal Wilkinson Power Dividers with In-/Reverse-Phase Using Lumped-Element Circuits Hiroyuki Mizuno, Tadashi Kawai, Isao Ohta (Univ. of Hyogo) MW2008-21 |
This paper treats a design method of lumped-element in-/reversed-phase Wilkinson power dividers with un-equal power spri... [more] | MW2008-21 pp.35-40 |
| ICD, IPSJ-ARC | 2008-05-13 10:30 |
Tokyo | An Evaluation of Barrier Synchronization Mechanism Considering Hierarchical Processor Grouping Kaito Yamada (Hitachi), Masayoshi Mase, Jun Shirako, Keiji Kimura (Waseda Univ.), Masayuki Ito, Toshihiro Hattori (Renesas), Hiroyuki Mizuno, Kunio Uchiyama (Hitachi), Hironori Kasahara (Waseda Univ.) |
In order to use a large number of processor cores in a chip, hierarchical coarse grain task parallel processing, which e... [more] | ICD2008-20 pp.19-24 |
|
| CPM, ICD | 2008-01-17 14:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg | [Special Invited Talk]
In-situ measurement of supply-noise maps with millivolt accuracy and nanosecond-order time resolution Yusuke Kanno, Yuki Kondoh (HCRL), Takahiro Irita, Kenji Hirose, Ryo Mori, Yoshihiko Yasu (Renesas Technology, Corp.), Shigenobu Komatsu, Hiroyuki Mizuno (HCRL) CPM2007-136 ICD2007-147 |
An in-situ measurement scheme for generating supply-noise maps, which can be conducted while running applications in pro... [more] | CPM2007-136 ICD2007-147 pp.47-52 |
| ICD, SDM | 2007-08-23 12:50 |
Hokkaido | Kitami Institute of Technology | [Special Invited Talk]
Past and Future of Dynamic Voltage Scaling Hiroyuki Mizuno (Hitachi) SDM2007-148 ICD2007-76 |
Effectiveness and issue for Dynamic Voltage Scaling (DVS) have been described. Both dynamic and leakage power reduction ... [more] | SDM2007-148 ICD2007-76 pp.41-46 |
| ICD, SDM | 2007-08-23 16:00 |
Hokkaido | Kitami Institute of Technology | [Panel Discussion]
Dynamic Voltage & Frequency Scaling ; A Key Technology for Deep Sub-100nm SoCs ! Tadayoshi Enomoto (Chuo Univ.), Naohiko Irie (Hitachi), Hiroshi Okano (Fujitsu), Shiro Sakiyama (Matsushita), Masakatsu Nakai (Sony), Koji Nii (Renesas Technology), Masahiro Nomura (NEC), Hiroyuki Mizuno (Hitachi) SDM2007-154 ICD2007-82 |
[more] | SDM2007-154 ICD2007-82 pp.75-78 |
| ICD | 2006-05-25 13:30 |
Hyogo | Kobe University | Hierarchical Power Distribution with dozens of power domain in 90-nm Low-power SoCs Yusuke Kanno (HCRL), Hiroyuki Mizuno (Hitachi), Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi (Renesas), Toshifumi Ishii (Hitachi ULSI), Tetsuya Yamada (HCRL), Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa (Renesas), Naohiko Irie (HCRL) |
[more] | ICD2006-26 pp.25-30 |
| AP, SAT (Joint) |
2006-05-19 11:40 |
Kagoshima | Kagoshima Univ. | Numerical analysis of electric field distribution near finite conducting plate in case of spherical wave incidence Hiroyuki Mizuno, Mitsuo Taguchi (Nagasaki Univ.) AP2006-23 |
[more] | AP2006-23 pp.83-86 |
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