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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2017-04-20 10:35 |
Tokyo | [Invited Lecture]
Sub-3 ns pulse with sub-100 uA switching of 1x-2x nm perpendicular MTJ for high-performance embedded STT-MRAM towards sub-20 nm CMOS Daisuke Saida, Saori Kashiwaad, Megumi Yakabe, Tadaomi Daibou, Junichi Ito, Hiroki Noguchi, Keiko Abe, Shinobu Fujita (Toshiba), Miyoshi Fukumoto, Shinji Miwa, Yoshishige Suzuki (Osaka Univ.)  ICD2017-2 |
[more] | ICD2017-2 pp.5-9 |
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| SDM | 2017-01-30 14:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Novel Voltage Controlled MRAM (VCM) with Fast Read/Write Circuits for Ultra Large Level Cache Yoichi Shiota (AIST), Hiroki Noguchi, Kazutaka Ikegami, Keiko Abe, Shinobu Fujita (Toshiba), Takayuki Nozaki, Shinji Yuasa (AIST), Yoshishige Suzuki (Osaka Univ.) SDM2016-135 |
In future processing system, the memory capacity of last level cache (LLC) must be increased, because LLC needs to cover... [more] | SDM2016-135 pp.21-24 |
| SDM | 2016-01-28 15:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
MTJ based "Normally-off processors" with thermal stability factor engineered perpendicular MTJ, L2 cache based on 2T-2MTJ cell, L3 and Last Level Cache based on 1T-1MTJ cell and novel error handling scheme Kazutaka Ikegami, Hiroki Noguchi, Satoshi Takaya, Chikayoshi Kamata, Minoru Amano, Keiko Abe, Keiichi Kushida, Eiji Kitagawa, Takao Ochiai, Naoharu Shimomura, Daisuke Saida, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) SDM2015-126 |
MTJ-based cache memory is expected to reduce processor power significantly. However, write energy increases rapidly for ... [more] | SDM2015-126 pp.27-30 |
| ICD | 2015-04-17 12:40 |
Nagano | [Invited Talk]
Low-power Embedded Perpendicular STT-MRAM Design for Cache Memory Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Chika Tanaka, Chikayoshi Kamata, Minoru Amano, Eiji Kitagawa, Naoharu Shimomura, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) ICD2015-10 |
[more] | ICD2015-10 pp.45-50 |
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| SDM | 2015-01-27 14:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Low power and high memory density STT-MRAM for embedded cache memory using advanced perpendicular MTJ integrations and asymmetric compensation techniques Kazutaka Ikegami, Hiroki Noguchi, Chikayoshi Kamata, Minoru Amano, Keiko Abe, Keiichi Kushida, Takao Ochiai, Naoharu Shimomura, Shogo Itai, Daisuke Saida, Chika Tanaka, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) SDM2014-142 |
Due to difficulty to increase clock frequency, recent processors increase cache memory to improve performance. However, ... [more] | SDM2014-142 pp.29-32 |
| ICD, CPSY | 2014-12-02 10:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Normally-Off Computing with Perpendicular STT-MRAM Hiroki Noguchi, Kazutaka Ikegami, Naoharu Shimomura, Tetsufumi Tanamoto, Junichi Ito, Shinobu Fujita (Toshiba) ICD2014-102 CPSY2014-114 |
[more] | ICD2014-102 CPSY2014-114 pp.107-112 |
| SDM | 2014-01-29 13:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Variable Nonvolatile Memory Arrays for Adaptive Computing Systems Hiroki Noguchi, Susumu Takeda, Kumiko Nomura, Keiko Abe, Kazutaka Ikegami, Eiji Kitagawa, Naoharu Shimomura, Junichi Ito, Shinobu Fujita (Toshiba) SDM2013-141 |
[more] | SDM2013-141 p.29 |
| MRIS, ITE-MMS | 2013-07-12 16:35 |
Tokyo | Chuo Univ. | Progress on STT MTJ writing Technology and the Effect on Normally-off Computing Systems Junichi Ito, Hiroaki Yoda, Shinobu Fujita, Naoharu Shimomura, Eiji Kitagawa, Keiko Abe, Kumiko Nomura, Hiroki Noguchi (Toshiba) MR2013-13 |
We propose a new processor using STT-MRAMs as cache memories. It enables “Normally-off computing”, where the processor i... [more] | MR2013-13 pp.37-41 |
| ICD | 2013-04-11 15:30 |
Ibaraki | Advanced Industrial Science and Technology (AIST) | [Invited Talk]
Novel Vertical Magnetization STT-MRAM Technologies for Reducing Power of High Performance Mobile Processors Shinobu Fujita, Keiko Abe, Hiroki Noguchi, Kumiko Nomura, Eiji Kitagawa, Naoharu Shimomura, Junichi Ito, Hiroaki Yoda (Toshiba) ICD2013-8 |
[more] | ICD2013-8 pp.39-40 |
| ICD, IPSJ-ARC | 2012-01-20 16:20 |
Tokyo | A 75-Variable MIQP Solver Processor for Real-Time Robot Control Masanori Nishino, Hiroki Noguchi, Yusuke Shimai, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2011-144 |
This paper describes a low-power eight-core Mixed Integer Quadric Programming (MIQP) solver processor VLSI for real-time... [more] | ICD2011-144 pp.103-107 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 10:05 |
Miyazaki | NewWelCity Miyazaki | A 40nm 144mW VLSI Processor for Realtime 60k Word Continuous Speech Reconginion Takanobu Sugahara, Guangji He, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) CPM2011-164 ICD2011-96 |
We have developed a low power VLSI chip for 60k-word real-time continuous speech recognition based on HMM(Hidden Markov ... [more] | CPM2011-164 ICD2011-96 pp.79-84 |
| ICD | 2011-04-19 09:30 |
Hyogo | Kobe University Takigawa Memorial Hall | 0.45-V Operating Vt-Variation Tolerant 9T/18T Dual-Port SRAM Koji Yanagida, Hiroki Noguchi, Shunsuke Okumura, Tomoya Takagi, Koji Kugata (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST), Hiroshi Kawaguchi (Kobe Univ.) ICD2011-8 |
We proposes a dependable dual-port SRAM with 9T/18T bitcell structure. The proposed SRAM has two operating modes: a 9T n... [more] | ICD2011-8 pp.43-48 |
| IPSJ-SLDM, SIP, IE, ICD [detail] | 2010-10-06 11:50 |
Chiba | Makuhari Messe, International Conference Hall | Data-Intensive Sound Acquisition with Data Aggregation Protocol for Microphone Array Networks Shintaro Izumi, Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shimpei Soda, Masahiko Yoshimoto, Hiroshi Kawaguchi (Kobe Univ.) SIP2010-67 ICD2010-81 IE2010-85 |
We propose a microphone array network that realizes ubiquitous sound acquisition. A number of nodes with sixteen microph... [more] | SIP2010-67 ICD2010-81 IE2010-85 pp.95-100 |
| ICD | 2009-04-14 10:40 |
Miyagi | Daikanso (Matsushima, Miyagi) | A 0.56-V 128kb 10T SRAM Using Column Line Assist (CLA) Scheme Shusuke Yoshimoto, Yusuke Iguchi, Shunsuke Okumura, Hidehiro Fujiwara, Hiroki Noguchi (Kobe Univ.), Koji Nii (Renesas Technology Corp.), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2009-6 |
We present a small-area 10T SRAM cell without half selection problem. As well, the proposed 10T cell achieves a faster a... [more] | ICD2009-6 pp.27-32 |
| ICD | 2009-04-14 11:05 |
Miyagi | Daikanso (Matsushima, Miyagi) | A 7T/14T Dependable SRAM and Its Array Structure to Avoid Half Selection Shunsuke Okumura, Hidehiro Fujiwara, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST-CREST) ICD2009-7 |
We propose a novel dependable SRAM with 7T cells and their array structure that avoids a half-selection problem. The dep... [more] | ICD2009-7 pp.33-38 |
| VLD, IPSJ-SLDM | 2008-05-09 14:35 |
Hyogo | Kobe Univ. | A Dependable SRAM with high-reliability mode and high-speed mode. Shunsuke Okumura, Hidehiro Fujiwara, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) |
We propose a novel dependable SRAM with 7T memory cell pair, and introduce a new concept, “quality of a bit （QoB）” for i... [more] | VLD2008-12 pp.31-36 |
| ICD, SDM | 2007-08-24 15:40 |
Hokkaido | Kitami Institute of Technology | An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi (Kobe Univ.), Koji Nii (Kobe Univ./Renesas Technology), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) SDM2007-167 ICD2007-95 |
This paper demonstrates that an 8T memory cell can be alternative design to a 6T cell in a future highly-integrated SRAM... [more] | SDM2007-167 ICD2007-95 pp.139-144 |
| ICD, ITE-IST | 2007-07-26 17:30 |
Hyogo | A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing Shunsuke Okumura, Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita (Kobe Univ.), Koji Nii (Kobe Univ./Renesas Technology), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2007-53 |
We propose a low-power non-precharge-type two-port SRAM for video processing. The proposed memory cell (MC) has ten tran... [more] | ICD2007-53 pp.95-100 |
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| ICD | 2007-04-12 13:50 |
Oita | A Novel Two-Port SRAM for Low Bitline Power Using Majority Logic and Data-Bit Reordering Hidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2007-7 |
[more] | ICD2007-7 pp.35-40 |
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| ICD, SDM | 2006-08-18 15:00 |
Hokkaido | Hokkaido University | A Vth-Variation-Tolerant SRAM with 0.3-V Minimum Operation Voltage for Memory-Rich SoC under DVS Environment Hiroki Noguchi (Kobe Univ.), Yasuhiro Morita (Kanazawa Univ.), Hidehiro Fujiwara, Kentaro Kawakami, Junichi Miyakoshi (Kobe Univ.), Shinji Mikami (Kanazawa Univ.), Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) |
[more] | SDM2006-152 ICD2006-106 pp.155-160 |
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