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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HWS, VLD | 2019-02-27 10:50 |
Okinawa | Okinawa Ken Seinen Kaikan | Spatial-Separable Convolution: Low memory CNN for FPGA Akira Jinguji, Masayuki Shimoda, Hiroki Nakahara (titech)  VLD2018-94 HWS2018-57 |
Object detection and image recognition using a Convolutional Neural Network (CNN) are used in embedded systems, which re... [more] | VLD2018-94 HWS2018-57 pp.7-12 |
| HWS, VLD | 2019-02-28 13:55 |
Okinawa | Okinawa Ken Seinen Kaikan | Model Compression for ECG Signals Outlier Detection Hardware trained by Sparse Robust Deep Autoencoder Naoto Soga, Shimpei Sato, Hiroki Nakahara (Titech) VLD2018-114 HWS2018-77 |
In recent years, portable electrocardiographs and wearable devices have begun to spread so that electrocar- diogram (ECG... [more] | VLD2018-114 HWS2018-77 pp.127-132 |
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2019-01-30 13:30 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | A CNN with a Noise Addition for Efficient Implementation on an FPGA Atsuki Munakata, Shimpei Satou, Hiroki Nakahara (Tokyo Tech) VLD2018-75 CPSY2018-85 RECONF2018-49 |
This article is a technical report without peer review, and its polished and/or extended version may be published elsewh... [more] | VLD2018-75 CPSY2018-85 RECONF2018-49 pp.19-24 |
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2019-01-30 13:55 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Filter-wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation Masayuki Shimoda, Youki Sada, Hiroki Nakahara (titech) VLD2018-76 CPSY2018-86 RECONF2018-50 |
[more] | VLD2018-76 CPSY2018-86 RECONF2018-50 pp.25-30 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-05 10:20 |
Hiroshima | Satellite Campus Hiroshima | An FPGA implementation of Tri-state YOLOv2 using Intel OpenCL Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (titech) RECONF2018-35 |
Since the convolutional neural network has a high-performance recognition accuracy, it is expected to implement variou... [more] |
RECONF2018-35 pp.7-12 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-05 13:00 |
Hiroshima | Satellite Campus Hiroshima | [Keynote Address]
Hiroki Nakahara (Titech) VLD2018-43 CPM2018-87 ICD2018-48 IE2018-66 CPSY2018-36 DC2018-29 RECONF2018-36 |
[more] | VLD2018-43 CPM2018-87 ICD2018-48 IE2018-66 CPSY2018-36 DC2018-29 RECONF2018-36 p.29(VLD), p.1(CPM), p.1(ICD), p.1(IE), p.1(CPSY), p.29(DC), p.13(RECONF) |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 10:55 |
Hiroshima | Satellite Campus Hiroshima | A Tiny Memory implementation on an FPGA using Feature-Map Separable Convolution Technique Akira Jinguji, Simpei Sato, Hiroki Nakahara (titech) RECONF2018-41 |
Object detection and image recognition using a convolutional neural network (CNN) are used in embedded systems. Embedded... [more] | RECONF2018-41 pp.39-44 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 11:20 |
Hiroshima | Satellite Campus Hiroshima | Hardware implementation of ECG signals outlier detector trained by Sparse Robust Deep Autoencoder Naoto Soga, Shimpei Sato, Hiroki Nakahara (Titech) RECONF2018-42 |
Current ECG outlier detection is rule-based, there are many false positives, and it is necessary to study a new outlier ... [more] | RECONF2018-42 pp.45-50 |
| RECONF | 2018-09-17 14:55 |
Fukuoka | LINE Fukuoka Cafe Space | A Performance Per Power Efficient Object Detector on an FPGA for Robot Operating System (ROS) Haoxuan Cheng, Shimpei Sato, Hiroki Nakahara (titech) RECONF2018-22 |
[more] | RECONF2018-22 pp.19-22 |
| RECONF | 2018-05-25 16:00 |
Tokyo | GATE CITY OHSAKI | Efficient Object Detection with Event-Driven camera and its implementation on an FPGA Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (titech) RECONF2018-17 |
We propose an object detection system using a sliding window method for an event-driven camera which outputs a subtrac... [more] |
RECONF2018-17 pp.81-86 |
| RECONF | 2018-05-25 16:25 |
Tokyo | GATE CITY OHSAKI | An Implementation of an Object Detector on an FPGA Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato (Titech) RECONF2018-18 |
[more] | RECONF2018-18 pp.87-92 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-18 09:40 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | All Binarized Conventional Neural Network and its Implementation on an FPGA
-- FPT2017 Design Competition Report -- Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (titech) VLD2017-63 CPSY2017-107 RECONF2017-51 |
[more] | VLD2017-63 CPSY2017-107 RECONF2017-51 pp.7-11 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-18 10:05 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | An Implementation of a Binarized Deep learning Neural Network on an FPGA using the Intel OpenCL Takumu Uyama, Tomoya Fujii, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara (Titech) VLD2017-64 CPSY2017-108 RECONF2017-52 |
[more] | VLD2017-64 CPSY2017-108 RECONF2017-52 pp.13-18 |
| RECONF | 2017-09-25 14:20 |
Tokyo | DWANGO Co., Ltd. | A Memory Reduction with Neuron Pruning for a Binarized Deep Convolutional Neural Network: Its FPGA Realization Tomoya Fujii, Shimpei Sato, Hiroki Nakahara (Tokyo Inst. of Tech.) RECONF2017-26 |
For a pre-trained deep convolutional neural network (CNN) for an embedded system, a high-speed and a low power consumpt... [more] |
RECONF2017-26 pp.25-30 |
| RECONF | 2017-09-26 10:00 |
Tokyo | DWANGO Co., Ltd. | GUINNESS: A GUI based Binarized Deep Neural Network Framework for an FPGA Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Shimpei Sato (Tokyo Inst. of Tech.) RECONF2017-31 |
[more] | RECONF2017-31 pp.51-56 |
| SDM, ICD, ITE-IST [detail] | 2017-08-02 10:15 |
Hokkaido | Hokkaido-Univ. Multimedia Education Bldg. | SDM2017-43 ICD2017-31 |
(To be available after the conference date) [more] | SDM2017-43 ICD2017-31 pp.101-106 |
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2017-07-27 15:45 |
Akita | Akita Atorion-Building (Akita) | Consideration of All Binarized Convolutional Neural Network Masayuki Shimoda, Tomoya Fujii, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara (Tokyo Inst. of Tech.) CPSY2017-28 |
A pre-trained convolutional neural network (CNN) is a feed-forward computation perspective, which is widely used for the... [more] | CPSY2017-28 pp.131-136 |
| RECONF, CPSY, DC, IPSJ-ARC (Joint) [detail] |
2017-05-22 14:20 |
Hokkaido | Noboribetsu-Onsen Dai-ichi-Takimoto-Kan | RECONF2017-2 |
[more] | RECONF2017-2 pp.7-11 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-24 15:25 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Implementation of Binarized Deep Neural Network for FPGA Considering Power Performance Enhancement Haruyoshi Yonekawa, Hiroki Nakahara (Tokyo Tech), Masato Motomura (Hokkaido Univ.) VLD2016-88 CPSY2016-124 RECONF2016-69 |
[more] | VLD2016-88 CPSY2016-124 RECONF2016-69 pp.127-132 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-24 15:50 |
Kanagawa | Hiyoshi Campus, Keio Univ. | A Memory Reduction with Neuron Pruning for a Convolutional Neural Network: Its FPGA Realization Tomoya Fujii, Simpei Sato, Hiroki Nakahara (Tokyo Tech), Masato Motomura (Hokkaido univ.) VLD2016-79 CPSY2016-115 RECONF2016-60 |
For a pre-trained deep convolutional neural network (CNN) aim at an embedded system, a high-speed and a low power consum... [more] | VLD2016-79 CPSY2016-115 RECONF2016-60 pp.55-60 |
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