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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2013-04-12 15:55 |
Ibaraki | Advanced Industrial Science and Technology (AIST) | [Invited Lecture]
A 250MHz 18Mb Full Ternary CAM with 0.3V Match Line Sense Amplifier in 65nm CMOS Isamu Hayashi, Teruhiko Amano, Naoya Watanabe, Yuji Yano, Yasuto Kuroda, Masaya Shirata, Katsumi Dosaka, Koji Nii, Hideyuki Noda, Hiroyuki Kawai (Renesas Electronics)  ICD2013-22 |
An 18Mb full ternary CAM with 0.3V match line sense amplifier (LV-MA) is designed and fabricated in 65nm bulk CMOS proce... [more] | ICD2013-22 pp.115-120 |
| SIS | 2008-06-13 12:50 |
Hokkaido | Application of the massively parallel embedded processor (MX) to real-time image processing Hiroyuki Yamasaki, Takeaki Sugimura, Hideyuki Noda, Osamu Yamamoto, Yoshihiro Okuno, Kazutami Arimoto (Renesas) SIS2008-20 |
We developed the massively parallel embedded processor core (MX core) for the SoC(System on Chip) building in as an acce... [more] | SIS2008-20 pp.33-38 |
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| ICD, ITE-CE | 2007-12-14 14:40 |
Kochi | A multi matrix-processor core architecture for real-time image processing SoC Katsuya Mizumoto, Takayuki Gyohten, Tetsushi Tanizaki, Soichi Kobayashi, Masami Nakajima, Hiroyuki Yamasaki, Hideyuki Noda, Motoki Higashida, Yoshihiro Okuno, Kazutami Arimoto (Renesas) ICD2007-138 |
This paper describes a real time image processing SoC(MX-SoC) with programmable multi matrix -processor(MX-Core) archite... [more] | ICD2007-138 pp.107-111 |
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| CPSY | 2007-10-25 13:00 |
Kumamoto | Kumamoto University | The application of the massively parallel processor based on the matrix architecture Katsuya Mizumoto, Hiroyuki Yamasaki, Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten, Masami Nakajima, Motoki Higashida, Yoshihiro Okuno, Kazutami Arimoto (Renesas) CPSY2007-24 |
We have developed programmable matrix-processor "MX-1". The MX-1 consists of MX-Core and a control CPU. The MX-Core is a... [more] | CPSY2007-24 pp.1-5 |
| CPSY | 2007-10-25 13:40 |
Kumamoto | Kumamoto University | The program development method of the massively parallel processor based on the matrix architecture. Hiroyuki Yamasaki, Katsuya Mizumoto, Hideyuki Noda, Tetsu Nishijima, Kanako Yoshida, Takeaki Sugimura, Takashi Kurafuji, Osamu Yamamoto, Yoshihiro Okuno, Kazutami Arimoto (Renesas) CPSY2007-25 |
Recently, the installed applications in the digital devices has been remarkably progressed. Considering these background... [more] | CPSY2007-25 pp.7-12 |
| CPSY | 2007-10-25 15:10 |
Kumamoto | Kumamoto University | Acceleration of Multimedia Data Processing with CAM-Enhanced Massive-Parallel SIMD Matrix Processor Takeshi Kumaki, Masakatsu Ishizaki, Masaharu Tagami, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.), Takayuki Gyohten, Hideyuki Noda, Yasuto Kuroda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito (Renesas Technology) CPSY2007-27 |
A multimedia processor requires four capabilities, fast processing, small area size, low power consumption and programma... [more] | CPSY2007-27 pp.19-24 |
| CPSY | 2007-10-25 15:50 |
Kumamoto | Kumamoto University | Acceleration of AES Encryption with CAM-Enhanced Massive-Parallel SIMD Matrix Processor Masakatsu Ishizaki, Takeshi Kumaki, Masaharu Tagami, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.), Takayuki Gyohten, Hideyuki Noda, Yoshihiro Okuno, Kazutami Arimoto (Renesas Technology) CPSY2007-28 |
We have previously reported that the Content Addressable Memory (CAM)-enhanced massive-parallel Single Instruction Multi... [more] | CPSY2007-28 pp.25-30 |
| ICD, ITE-CE | 2006-12-15 12:05 |
Hiroshima | Multiple CAM Matches and Self-adapting Codeword Table for Optimized Real-time Huffman Encoding Masakatsu Ishizaki, Takeshi Kumaki, Yutaka Kono, Masaharu Tagami, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.), Yasuto Kuroda, Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito (Renesas Technology Corp.) |
[more] | ICD2006-165 pp.125-130 |
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| ICD, SIP, IE, IPSJ-SLDM | 2006-10-26 11:30 |
Miyagi | Super parallel SIMD processor with CAM based high-speed pattern matching capability Yutaka Kono, Takeshi Kumaki, Masakatsu Ishizaki, Masaharu Tagami, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.), Takayuki Gyohten, Hideyuki Noda, Yasuto Kuroda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito (Renesas) |
A super parallel SIMD processor has been developed for handling the increasing amount of multimedia data efficiently. ... [more] |
SIP2006-90 ICD2006-116 IE2006-68 pp.39-44 |
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| ICD, SDM | 2006-08-17 09:05 |
Hokkaido | Hokkaido University | A super parallel SIMD processor with Time/Space conversion Bus Bridge on the Matrix Architecture Tetsushi Tanizaki, Takayuki Gyohten, Hideyuki Noda, Masami Nakajima, Katsuya Mizumoto, Katsumi Dosaka (Renesas) |
A super parallel SIMD processor based on the matrix architecture which consists of 2k processors, embedded SRAM, and tim... [more] | SDM2006-125 ICD2006-79 pp.1-6 |
| ICD | 2006-05-25 13:00 |
Hyogo | Kobe University | A 40GOPS 250mW Massively Parallel Processor Based on Matrix Architecture
-- A Very High Performance Processor IP for Mobile System-on-Chips -- Kiyoshi Nakata, Masami Nakajima, Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten (Renesas) |
We have developed a massively parallel processor based on Matrix architecture. This architecture achieved 40GOPS of 16-b... [more] | ICD2006-25 pp.19-23 |
| SIP, ICD, IE, IPSJ-SLDM | 2005-10-20 16:10 |
Miyagi | Ichinobo, Sakunami-Spa | A Soft-Error-Immune TCAM Archiecture with Associated Embedded DRAM Yuji Yano, Hideyuki Noda, Katsumi Dosaka, Fukashi Morishita, Kazunari Inoue, Toshiyuki Ogawa, Kazutami Arimoto (Renesas) |
[more] | SIP2005-112 ICD2005-131 IE2005-76 pp.101-105 |
| SIP, ICD, IE, IPSJ-SLDM | 2005-10-20 16:30 |
Miyagi | Ichinobo, Sakunami-Spa | A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI Takayuki Gyohten, Fukashi Morishita, Hideyuki Noda (Renesas Technology Corp.), Mako Okamoto (Daioh Electric Corp.), Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto (Renesas Technology Corp.) |
We propose a novel capacitorless twin-transistor random access memory (TTRAM). The 2Mb test device has been fabricated o... [more] | SIP2005-113 ICD2005-132 IE2005-77 pp.107-112 |
| RECONF | 2005-05-13 13:00 |
Kyoto | Kyoto University | [Invited Talk]
Programmable Device Technologies for SoC Embedded Applications Masami Nakajima, Hideyuki Noda, Kazutami Arimoto (Renesas) |
SoC for digital consumer market requires short time and low cost of development and easy system change. SoC development ... [more] | RECONF2005-21 pp.37-42 |
| RECONF | 2005-05-13 14:00 |
Kyoto | Kyoto University | A performance evaluation of SIMD type accelerator for JPEG2000 application Fumiaki Senoue, Kozo Komoda, Masahiro Iida, Morihiro Kuga (Kumamoto Univ.), Hideyuki Noda, Masami Nakajima (Renesas), Toshinori Sueyoshi (Kumamoto Univ.) |
Embedded processor is often complemented with dedicated hardware or reconfigurable logic in order to execute complicated... [more] | RECONF2005-22 pp.43-48 |
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