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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 21 - 39 of 39 [Previous]  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
MW 2011-12-16
14:30
Yamaguchi Yamaguchi University Effect of Anomalous Skin Effect on Transmission-Line Loss
Akira Tsuchiya, Hidetoshi Onodera (Kyoto Univ.) MW2011-139
As the progress of technology scaling, the target frequency of high speed integrated circuits
has reached over 100GHz.
... [more]
MW2011-139
pp.77-81
ICD 2011-12-16
09:55
Osaka   A 65-nm Radiation-Hard Flip-Flop Tolerant to Multiple Cell Upsets
Ryosuke Yamamoto, Chikara Hamanaka (Kyoto Inst. of Tech.), Jun Furuta (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Hidetoshi Onodera (Kyoto Univ.) ICD2011-129
MCUs in redundant FFs is a dominant factor in a current deep-submicron process. A layout structure to avoid MCUs is prop... [more] ICD2011-129
pp.131-136
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2011-11-29
15:05
Miyazaki NewWelCity Miyazaki Multi-core LSI Lifetime Extension by NBTI-Recovery-based Self-healing
Takashi Matsumoto, Hiroaki Makino (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Inst. Tech.), Hidetoshi Onodera (Kyoto Univ.) CPM2011-160 ICD2011-92
Designing reliable systrems has become more difficult in recent years. Negative-Bias-Temperature-In-stability (NBTI) is ... [more] CPM2011-160 ICD2011-92
pp.59-63
VLD 2011-03-02
17:00
Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center [Fellow Memorial Lecture] Understanding CMOS Variability for More Moore
Hidetoshi Onodera (Kyoto Univ./JST) VLD2010-124
With the device dimensions in the nanometer regime,
variability becomes a serious concern in LSI design.
Aggressive sc... [more]
VLD2010-124
p.49
ICD 2010-12-16
15:10
Tokyo RCAST, Univ. of Tokyo [Poster Presentation] A 65nm CMOS High-Speed and High-Fidelity NBTI Recovery Sensor
Takashi Matsumoto, Hiroaki Makino (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Inst. Tech.), Hidetoshi Onodera (Kyoto Univ.) ICD2010-104
We proposed an NBTI-recovery sensor with 400ns measurement delay. This sensor contains many unit cells. One unit cell in... [more] ICD2010-104
pp.55-58
ICD 2010-12-17
10:55
Tokyo RCAST, Univ. of Tokyo Development of Procedure for Modeling MOSFET Compatible with ITRS -- Noise and I-V Characteristics Modeling for RF/Analog MOSFET --
Sin-Nyoung Kim, Akira Tsuchiya, Hidetoshi Onodera (Kyoto Univ.) ICD2010-119
A procedure for modeling MOSFET compatible with ITRS is proposed. Compared to the PTM, this work focuses on how to gener... [more] ICD2010-119
pp.119-123
ICD, SDM 2010-08-27
14:10
Hokkaido Sapporo Center for Gender Equality A 65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop Capable of Protecting Soft Errors on the C-element
Jun Furuta (Kyoto Univ.), Chikara Hamanaka, Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Hidetoshi Onodera (Kyoto Univ.) SDM2010-146 ICD2010-61
 [more] SDM2010-146 ICD2010-61
pp.121-124
VLD 2010-03-10
15:25
Okinawa   Generation Mechanism of SEU and MCU Caused by Parasitic Lateral Bipolar Transitstors
Chikara Hamanaka (Kyoto Institute of Tech.), Jun Furuta, Hiroaki Makino (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Institute of Tech.), Hidetoshi Onodera (Kyoto Univ./JST, CREST) VLD2009-103
Tolerance for soft-error decreases as integration advances. SEU(Single Event Upset), flipping one bit
and MCU(Multi-Cel... [more]
VLD2009-103
pp.25-30
ICD 2009-12-15
16:35
Shizuoka Shizuoka University (Hamamatsu) Bandwidth Enhancement for TIA with Mutually Coupled Inductors
Yoshihiro Okumura (Kyoto Univ.), Makoto Nakamura (NTT), Keiji Kishine (University of Shiga Prefecture), Akira Tsuchiya, Hidetoshi Onodera (Kyoto Univ.) ICD2009-104
A bandwidth enhancement technique for TransImpedance Amplifier (TIA) is proposed.
Bandwidth is an important issue for C... [more]
ICD2009-104
pp.157-161
ICD, ITE-IST 2008-10-23
10:20
Hokkaido Hokkaido University [Invited Talk] Toward Variability-Aware Design
Hidetoshi Onodera (Kyoto Univ./JST) ICD2008-73
 [more] ICD2008-73
pp.83-88
ICD, ITE-IST 2008-10-23
16:05
Hokkaido Hokkaido University [Panel Discussion] Challenges and Future of Analog Circuit Design using Sub-100nm CMOS Devices
Shoji Kawahito (Shizuoka Univ.), Shigetoshi Sugawa (Tohoku Univ.), Tatsuya Ohguro (Toshiba), Hidetoshi Onodera (Kyoto Univ.), Kunihiko Goto (Fujitsu Labs.), Toshihiko Hamasaki (TI), Shiro Dosho (Panasonic)
 [more]
VLD, ICD 2008-03-07
13:50
Okinawa TiRuRu A Low-cost Speed and Yield Enhancement Method Using Embedded Delay Detectors on FPGAs
Yohei Kume, Yuuri Sugihara, Ngo Cam Lai, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ.) VLD2007-163 ICD2007-186
This paper shows the principle and architecture of
a low-cost speed and yield enhancement
method using enbedded dela... [more]
VLD2007-163 ICD2007-186
pp.41-46
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]
2007-11-20
16:00
Fukuoka Kitakyushu International Conference Center Track Swapping on Critical Paths Utilizing Random Variations for FPGAs to Enhance Speed and Yield
Yuuri Sugihara, Youhei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ.) RECONF2007-34
FPGAs in future deep submicron fabrication process will suffer from drastic speed and yield loss caused by device variat... [more] RECONF2007-34
pp.13-18
VLD, IPSJ-SLDM 2007-05-11
14:35
Kyoto Kyodai Kaikan Effect of Dummy Fill on High-Frequency Characteristics of On-Chip Interconnects
Akira Tsuchiya, Hidetoshi Onodera (Kyoto Univ.) VLD2007-16
This paper reports measurement results of on-chip interconnects with CMP dummy fill.
CMP dummy fill is a floating metal... [more]
VLD2007-16
pp.55-59
RECONF 2006-05-19
11:30
Miyagi TOHOKU UNIVERSITY Speed enhancement of FPGAs by reconfigration utilizing variations within a chip
Kosuke Ogata, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ.)
 [more] RECONF2006-14
pp.19-24
ICD, VLD 2006-03-10
14:25
Okinawa   A reconfigurable circuit to utilize and compensate device variations
Manabu Kotani, Kazuya Katsuki, Kosuke Ogata, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ.)
This paper provides the principle and architecture of a reconfigurable circuit utilizing Within-Die variaitions and sho... [more] VLD2005-130 ICD2005-247
pp.49-54
VLD, ICD, DC, IPSJ-SLDM 2005-12-01
16:15
Fukuoka Kitakyushu International Conference Center Deterministic/Probablistic Noise and Bit Error Rate Modeling on On-chip Global interconnect
Yoichi Yuyama, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ.)
 [more] VLD2005-73 ICD2005-168 DC2005-50
pp.73-78
VLD, ICD 2005-03-10
- 2005-03-11
Okinawa Mielparque Okinawa Analytical Performance Estimation of On-chip Global Interconnects for High-speed Signaling
Akira Tsuchiya (Kyoto Univ.), Masanori Hashimoto (Osaka Univ.), Hidetoshi Onodera (Kyoto Univ.)
 [more] VLD2004-145 ICD2004-241
pp.49-54
VLD, ICD 2005-03-10
- 2005-03-11
Okinawa Mielparque Okinawa An Energy Reduction Technique with Task Relocation Considering Energy Minimum Execution Frequency for Multiprocessor Systems
Yutetsu Takatsukasa, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ.)
 [more] VLD2004-143 ICD2004-239
pp.37-42
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