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Committee Date Time Place Paper Title / Authors Abstract Paper #
Tokyo Keio Univ. Hiyoshi Campus Model Checking of Cycle Accurate Hardware Behavior Models with Instantaneous Communication
Hirohisa Fujita, Masahiko Hamada, Tadaaki Tanimoto, Akio Nakata, Teruo Higashino (Osaka Univ.)
Wiring delay imposes a limitation on
increase of clock frequency.
Therefore, instantaneous communications
consuming ... [more]
VLD2006-98 CPSY2006-69 RECONF2006-69
RECONF 2005-11-30
Fukuoka Kitakyushu International Conference Center A New Design Method for Implementing Real-Time Embedded Systems on Dynamically Reconfigurable Processors
Ryo Nakahashi, Tomoya Kitani (Osaka Univ.), Keiichi Yasumoto (NAIST), Akio Nakata, Teruo Higashino (Osaka Univ.)
The dynamically reconfigurable processor (DRP, hereafter) has multiple different circuit patterns called contexts which ... [more] RECONF2005-58
VLD, ICD, DC, IPSJ-SLDM 2005-12-02
Fukuoka Kitakyushu International Conference Center A Method for Allocating Bus Transfer and Task Execution Cycles Based on Scenarios
Seiji Yamaguchi, Tadaaki Tanimoto, Akio Nakata, Teruo Higashino (Osaka Univ.)
In designing a bus system, it is important to derive a real-time constraint (the number of available cycles) for each ta... [more] VLD2005-80 ICD2005-175 DC2005-57
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