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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 15:00 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Easily-testable Carry Select Adder with Online Error Detection Capability Nobutaka Kito (Chukyo Univ.)  VLD2015-72 DC2015-68 |
An easily testable multi-block carry select adder with online error detection capability is proposed. An easily testable... [more] | VLD2015-72 DC2015-68 pp.225-230 |
| CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] | 2015-03-07 13:25 |
Kagoshima | Design and Evaluation of a Floating-point Multiplier with Online Error Detection by Partial Duplication Nobutaka Kito (Chukyo Univ.), Kazushi Akimoto, Naofumi Takagi (Kyoto Univ.) CPSY2014-181 DC2014-107 |
A floating-point multiplier with reduced precision error detection is proposed. It uses a truncated multiplier for chec... [more] |
CPSY2014-181 DC2014-107 pp.125-130 |
|
| DC | 2014-06-20 15:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Floating-point Multiplier with Reduced Precision Error Checking by Partial Duplication Nobutaka Kito (Chukyo Univ.), Kazushi Akimoto, Naofumi Takagi (Kyoto Univ.) DC2014-15 |
We propose a floating-point multiplier with reduced precision error checking. The multiplier uses a truncated multiplie... [more] |
DC2014-15 pp.33-38 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] | 2013-03-14 15:05 |
Nagasaki | Self-Checking Carry Look-ahead Adder by Carry-bit Duplication Akihiro Mitoma (Kyoto Univ.), Nobutaka Kito (Chukyo Univ.), Naofumi Takagi (Kyoto Univ.) CPSY2012-98 DC2012-104 |
We propose a self-checking carry look-ahead adder, which can detect errors caused by a single stuck-at fault in the adde... [more] | CPSY2012-98 DC2012-104 pp.277-282 |
|
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] | 2013-03-14 15:30 |
Nagasaki | Multiplier with concurrent error detection by particial duplication Kazushi Akimoto (Kyoto Univ.), Nobutaka Kito (Cyukyo Univ.), Naofumi Takagi (Kyoto Univ.) CPSY2012-99 DC2012-105 |
We propose a multiplier with concurrent error detection, which can detect the error more than the designated numerical v... [more] | CPSY2012-99 DC2012-105 pp.283-287 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 16:50 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Design Method of Fault-Secure Parallel Prefix Adders by Carry-Bit Duplication Nobutaka Kito (Chukyo Univ.), Naofumi Takagi (Kyoto Univ.) VLD2012-106 DC2012-72 |
We show a design method of fault-secure parallel prefix adders with various prefix structures. Adders by the method gen... [more] |
VLD2012-106 DC2012-72 pp.273-278 |
| SCE | 2012-07-19 11:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | SFQ Bit-Slice Floating Point Adder Yukio Ohmomo, Yohei Naruse (Kyoto Univ.), Nobutaka Kito (Chukyo Univ.), Naofumi Takagi, Kazuyoshi Takagi (Kyoto Univ.) SCE2012-11 |
Single Flux Quantum (SFQ) circuits operate at high-speed with low-power consumption. A Large-Scale Reconfigurable Data ... [more] |
SCE2012-11 pp.13-17 |
| SCE | 2012-07-19 11:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Design of a 2bit Bit-Slice Half-Precision Floating-Point Multiplier Using SFQ Circuits Yohei Naruse (Kyoto Univ.), Nobutaka Kito (Chukyo Univ.), Naofumi Takagi (Kyoto Univ.) SCE2012-12 |
Single flux quantum (SFQ) circuits are expected as next-generation circuits. Arithmetic circuits using SFQ circuits ha... [more] |
SCE2012-12 pp.19-23 |
| SCE | 2011-07-13 15:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | High-Throuput Bit-Slice Multipliers Using SFQ Circuits Yohei Naruse, Nobutaka Kito, Naofumi Takagi (Kyoto Univ.) SCE2011-9 |
Single flux quantum (SFQ) circuits are expected as next-generation circuits. Arithmetic circuits using SFQ circuits have... [more] | SCE2011-9 pp.47-52 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] | 2011-03-18 10:55 |
Okinawa | Modeling of Timing Faults and Test Generation for Single Flux Quantum Logic Circuits Nobutaka Kito (Kyoto Univ.), Kazuyoshi Takagi (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.) CPSY2010-74 DC2010-73 |
Single Flux Quqntum(SFQ) logic circuits are expected to achieve ultra-high-performance computers with low power. For r... [more] |
CPSY2010-74 DC2010-73 pp.51-56 |
|
| SCE | 2010-07-22 11:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Fault Modeling and Test Generation for Single Flux Quantum Logic Circuits Nobutaka Kito (Kyoto Univ.), Masamitsu Tanaka, Kazuyoshi Takagi (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.) SCE2010-19 |
This report discusses fault modeling and test generation for Single Flux Quqntum(SFQ) logic circuits. SFQ circuits ar... [more] |
SCE2010-19 pp.31-35 |
| DC | 2008-06-20 14:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg | Test generation for multi-operand adders consisting of full adders Nobutaka Kito, Naofumi Takagi (Nagoya Univ.) DC2008-14 |
Level-testability of multi-operand adders consisting of carry save adders is shown by showing test design for it. Carry ... [more] | DC2008-14 pp.19-22 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-21 14:15 |
Fukuoka | Kitakyushu International Conference Center | A design method for easily testable multipliers adaptable to various structures of partial product addition Nobutaka Kito, Naofumi Takagi (Nagoya Univ.) VLD2007-83 DC2007-38 |
We propose a design method for easily testable multipliers. We construct partial product adders of a multiplier with t... [more] |
VLD2007-83 DC2007-38 pp.7-12 |
| ICD, VLD | 2007-03-09 08:40 |
Okinawa | Mielparque Okinawa | Easily Testable Multiplier with 4-2 Adder Tree Nobutaka Kito, Kensuke Hanai, Naofumi Takagi (Nagoya Univ.) |
The growth of the scale of VLSI designs makes test cost of VLSI chips expensive. Techniques of test cost reduction are r... [more] | VLD2006-140 ICD2006-231 pp.1-6 |
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