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DC 2014-06-20
14:30		 Tokyo Kikai-Shinko-Kaikan Bldg. Capture Power Evaluation for A Low Power BIST Method Using A TEG Chip
Toshiya Nishida (Kyushu Inst. of Tech.), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.) DC2014-13		 Voltage drop by a momentary current change during capture cycles in scan-based testing brings an increase in path delay ... [more] DC2014-13
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