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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-25 14:50 |
Online | Online | Efficient Attention Mechanism by Softmax Function with Trained Coefficient Kaito Hirota (UT), O'uchi Shinichi (AIST), Fujita Masahiro (UT)  VLD2020-48 CPSY2020-31 RECONF2020-67 |
BERT is a neural network model which has accomplished state-of-the-art performance on eleven natural language processing... [more] | VLD2020-48 CPSY2020-31 RECONF2020-67 pp.52-57 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2020-11-17 09:55 |
Online | Online | Efficient computation of inductive invariant through flipflop selection Fudong Wang, Masahiro Fujita (U-Tokyo) VLD2020-20 ICD2020-40 DC2020-40 RECONF2020-39 |
As we all know, verification plays more and more important role in VLSI design and manufacture. However, it always takes... [more] | VLD2020-20 ICD2020-40 DC2020-40 RECONF2020-39 pp.54-59 |
| RECONF | 2020-09-11 15:35 |
Online | Online | Inductive Invariant Generation Based on Binary Decision Diagram and its Application to Logic Synthesis Liu ZiHao, Miyasaka Yukio, Fujita Masahiro (UT) RECONF2020-28 |
In this paper, we mainly focus on inductive invariant generation using binary decision diagram (BDD), and its applicatio... [more] | RECONF2020-28 pp.54-59 |
| HWS, VLD [detail] | 2020-03-04 10:55 |
Okinawa | Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
An Automatic Method to Generalize Matrix-Vector Multiplication with Multiple Processors Considering the Efficiency of the Communications Akihiro Goda, Masahiro Fujita (UT) VLD2019-97 HWS2019-70 |
[more] | VLD2019-97 HWS2019-70 pp.19-24 |
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2020-01-24 14:20 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | An Approach to Approximate Multiplier Optimization Xinpei Zhang, Amir Masoud Gharehbaghi, Masahiro Fujita (Univ. Tokyo) VLD2019-88 CPSY2019-86 RECONF2019-78 |
[more] | VLD2019-88 CPSY2019-86 RECONF2019-78 pp.205-210 |
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2020-01-24 14:45 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Partial synthesis method based on Column-wise verification for integer multipliers Jian Gu, Amir Masoud Gharehbaghi, Masahiro Fujita (UTokyo) VLD2019-89 CPSY2019-87 RECONF2019-79 |
Partial logic synthesis is a method that most parts of the target circuits are fixed and the missing portions can be log... [more] | VLD2019-89 CPSY2019-87 RECONF2019-79 pp.211-216 |
| VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-13 11:20 |
Ehime | Ehime Prefecture Gender Equality Center | A New ATPG-based Logic Optimization Method by Removing the Redundant Multiple Faults Peikun Wang, Amir Masaud Gharehbaghi, Masahiro Fujita (The Univ. of Tokyo) VLD2019-32 DC2019-56 |
In this paper, we propose a new ATPG-based logic optimization method by removing the redundant multiple faults. In order... [more] | VLD2019-32 DC2019-56 pp.19-22 |
| VLD, IPSJ-SLDM | 2019-05-15 15:25 |
Tokyo | Ookayama Campus, Tokyo Institute of Technology | SRAM-Based Synthesis for Multi-Output Gates Xingming Le, Amir Masoud Gharehbaghi, Masahiro Fujita (The Univ. of Tokyo) VLD2019-4 |
Conventionally a circuit is represented as a network of single-output gates. In this paper, we propose an implementation... [more] | VLD2019-4 pp.25-30 |
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2019-01-30 11:20 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita (UTokyo) VLD2018-74 CPSY2018-84 RECONF2018-48 |
This paper proposes an incremental ATPG method to deal with multiple stuck-at faults. In order to generate the test set ... [more] | VLD2018-74 CPSY2018-84 RECONF2018-48 pp.13-18 |
| VLD, IPSJ-SLDM | 2018-05-16 13:30 |
Fukuoka | Kitakyushu International Conference Center | Partial logic synthesis by using sum of products or product of sums based quantified boolean formulae Xiaoran Han, Amir Masoud Gharehbaghi, Masahiro Fujita (UTokyo) VLD2018-1 |
documentclass[a4paper,11pt]{jarticle} usepackage{kws} usepackage{amssymb} usepackage{amsmath,array,graphicx} ... [more] |
VLD2018-1 pp.1-5 |
| ICD | 2018-04-20 13:50 |
Tokyo | [Invited Talk]
Memory LSI using crystalline oxide semiconductor FET Jun Koyama, Takako Seki, Yuto Yakubo, Satoru Ohshita, Kazuma Furutani, Takahiko Ishizu, Tomoaki Atsumi, Yoshinori Ando, Daisuke Matsubayashi, Kiyoshi Kato, Takashi Okuda (SEL), Masahiro Fujita (The Univ. of Tokyo), Shunpei Yamazaki (SEL) ICD2018-12 |
FETs fabricated with a c-axis aligned crystalline In-Ga-Zn oxide semiconductor (CAAC-IGZO) have an extremely low off-sta... [more] | ICD2018-12 pp.47-52 |
|
| VLD, IPSJ-SLDM | 2017-05-10 13:30 |
Fukuoka | Kitakyushu International Conference Center | VLD2017-1 |
In this paper, we present techniques to automatically generate high-level C description after ECO (Engineering Change Or... [more] | VLD2017-1 pp.1-6 |
| ICD | 2017-04-21 13:50 |
Tokyo | [Invited Lecture]
Embedded Memory and ARM Cortex-M0 Core Using 60-nm CAAC-IGZO FET Integrated with 65-nm Si CMOS Tatsuya Onuki, Atsuo Isobe, Yoshinori Ando, Satoru Okamoto, Kiyoshi Kato (Semiconductor Energy Laboratory), T R Yew, Chen Bin Lin, J Y Wu, Chi Chang Shuai, Shao Hui Wu (United Microelectronics Corporation), James Myers (ARM), Klaus Doppler (Nokia Technologies), Masahiro Fujita (The Univ. of Tokyo), Shunpei Yamazaki (Semiconductor Energy Laboratory) ICD2017-17 |
[more] | ICD2017-17 pp.89-93 |
|
| VLD, CAS, MSS, SIP | 2016-06-16 10:10 |
Aomori | Hirosaki Shiritsu Kanko-kan | Automatic Test Pattern Generation for Multiple Stuck-At Faults: When Testing for Single Faults is Insufficient Conrad JinYong Moore, Amir Masoud Gharehbaghi, Masahiro Fujita (Univ. of Tokyo) CAS2016-3 VLD2016-9 SIP2016-37 MSS2016-3 |
As fabricated circuitry gets larger and denser, modern industrial ATPG techniques which focus on the detection of single... [more] | CAS2016-3 VLD2016-9 SIP2016-37 MSS2016-3 pp.13-18 |
| ICD | 2015-04-17 10:50 |
Nagano | [Invited Talk]
A 128kb 4bit/cell Nonvolatile Memory with Crystalline In-Ga-Zn Oxide FET Using Vt Cancel Write Method Takanori Matsuzaki, Tatsuya Onuki, Shuhei Nagatsuka, Hiroki Inoue, Takahiko Ishizu, Yoshinori Ieda, Masayuki Sakakura, Tomoaki Atsumi, Yutaka Shionoiri, Kiyoshi Kato, Takashi Okuda, Yoshitaka Yamamoto (SEL), Masahiro Fujita (The Univ. of Tokyo), Jun Koyama, Shunpei Yamazaki (SEL) ICD2015-9 |
A 128kbit 4bit/cell memory is achieved by a nonvolatile oxide semiconductor RAM test chip with a c-axis aligned crystall... [more] | ICD2015-9 pp.39-44 |
|
| ICD, SDM | 2014-08-04 15:45 |
Hokkaido | Hokkaido Univ., Multimedia Education Bldg. | [Invited Talk]
A 32-bit CPU with Zero Standby Power and 1.5-clock Backup/2.5-clock Restore Achieved by Utilizing a 180-nm Crystalline Oxide Semiconductor Transistor Jun Koyama, Atsuo Isobe, Hikaru Tamura, Kiyoshi Kato, Takuro Ohmaru, Wataru Uesugi, Takahiko Ishizu, Kazuaki Ohshima, Yasutaka Suzuki, Naoaki Tsutsui, Tomoaki Atsumi, Yutaka Shionoiri, Yukio Maehashi (SEL), Masahiro Fujita (Univ. of Tokyo), Shunpei Yamazaki (SEL) SDM2014-70 ICD2014-39 |
A flip-flop achieving high-speed backup utilizing a Si transistor and long-term retention with zero standby power by mea... [more] | SDM2014-70 ICD2014-39 pp.45-50 |
| IPSJ-SLDM, VLD | 2012-05-30 15:45 |
Fukuoka | Kitakyushu International Conference Center | High-level Design Debugging Using Potential Dependence Shohei Ono, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo) VLD2012-4 |
As high-level design draws more attention and has been adopted more widely, verification and debugging for high- level d... [more] | VLD2012-4 pp.19-24 |
| IPSJ-SLDM, VLD | 2012-05-31 11:20 |
Fukuoka | Kitakyushu International Conference Center | Statistical Analysis and its Hardware Implementation on Simulation Results of Systems with Uncertain Inputs Kosuke Oshima, Shohei Ono, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo) VLD2012-10 |
Statistical model checking is a method to analyze systems where variables have some uncertainty. It can be used to check... [more] | VLD2012-10 pp.55-60 |
| VLD | 2012-03-06 15:05 |
Oita | B-con Plaza | High-Level Synthesis for Mixed Behavioral-Level/RTL Design Descriptions Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo) VLD2011-128 |
It is widely known that high-level synthesis technology can improve the design productivity dramatically by raising the ... [more] | VLD2011-128 pp.49-54 |
| RECONF | 2011-05-13 09:15 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | * Akira Fukui, Masahiro Fujita (Tokyo University) RECONF2011-12 |
Smith-Waterman Algorithm is utilized for alignment of DNA and protein sequences. When an un- known sample of DNA or pro... [more] |
RECONF2011-12 pp.67-72 |
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