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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 21 - 40 of 46 [Previous]  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-08
15:55
Kumamoto Kumamoto-Kenminkouryukan Parea Max Length and Length Difference Minimization for Set Pair Routing Problem with ILP
Shutaro Hara, Kunihiro Fujiyoshi (TUAT) VLD2017-60 DC2017-66
Set pair routing is the problem to minimize the maximum difference of paths (length difference) that one to one connecte... [more] VLD2017-60 DC2017-66
pp.241-246
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-08
16:20
Kumamoto Kumamoto-Kenminkouryukan Parea An Efficient Search Method on Stacked Rectangular Dissections
Masaki Yokota, Kunihiro Fujiyoshi (TUAT) VLD2017-61 DC2017-67
For layout design of 3D-LSI, a stacked-rectangular-dissection,
which consists of several rectangular dissections
as... [more]
VLD2017-61 DC2017-67
pp.247-252
VLD, IPSJ-SLDM 2017-05-10
15:00
Fukuoka Kitakyushu International Conference Center A Method of Layout Pattern Classification Using Clustering
Shuhei Ishino, Mitsuru Hasegawa, Kunihiro Fujiyoshi (TUAT) VLD2017-2
Layout of VLSI circuits is designed according to design rule, however, hotspots may remain due to feature size shrinking... [more] VLD2017-2
pp.7-12
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-29
10:55
Osaka Ritsumeikan University, Osaka Ibaraki Campus Length Difference Minimization with Exchanging Pin Pair for Set Pair Routing Problem
Shutaro Hara, Kunihiro Fujiyoshi (TUAT) VLD2016-57 DC2016-51
Set pair routing is the problem to minimize the maximum difference of paths(length difference) that one to one connected... [more] VLD2016-57 DC2016-51
pp.79-84
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-29
11:20
Osaka Ritsumeikan University, Osaka Ibaraki Campus SADP-Cut Aware Two-color Grid Routing
Hatsuhiko Miura, Mitsuru Hasegawa, Kunihiro Fujiyoshi (TUAT) VLD2016-58 DC2016-52
Self-Aligned Double Patterning (SADP) is one of the promising manufacturing option to overcome the limit of miniaturizat... [more] VLD2016-58 DC2016-52
pp.85-90
VLD, IPSJ-SLDM 2016-05-11
10:25
Fukuoka Kitakyushu International Conference Center Self-Aligned Double Patterning-Aware Two-color Grid Routing
Hatsuhiko Miura, Mitsuru Hasegawa, Taku Hirukawa, Kunihiro Fujiyoshi (TUAT) VLD2016-2
Self-Aligned Double Patterning (SADP) is one of the promising manufacturing option to overcome the limit of miniaturizat... [more] VLD2016-2
pp.5-10
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-02
11:15
Nagasaki Nagasaki Kinro Fukushi Kaikan Improved Method of Simulated Annealing for Unreachable Solution Space
Hiroyuki Nakano, Kunihiro Fujiyoshi (TUAT) VLD2015-45 DC2015-41
Simulated Annealing is a universal probabilistic metaheuristic for the general optimization problem of locating a good a... [more] VLD2015-45 DC2015-41
pp.45-50
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-02
16:45
Nagasaki Nagasaki Kinro Fukushi Kaikan Layout Decomposition into L-Shaped Parts for Variable Shaped-Beam Mask Writer
Katsuya Hoshi, Kunihiro Fujiyoshi (TUAT) VLD2015-52 DC2015-48
Since electron beam mask writers for LSI mask fabrication can only expose a rectangle shaped-beam, a layout pattern has ... [more] VLD2015-52 DC2015-48
pp.87-92
NLP, CAS 2015-10-06
09:30
Hiroshima Aster Plaza Polygon Fracture Method Considering Maximum Shot Size for Variable Shaped-Beam Mask Writing
Mitsuru Hasegawa, Kunihiro Fujiyoshi (TUAT) CAS2015-34 NLP2015-95
Since variable shaped-beam mask writing machines for LSI mask production can expose a rectangle shaped-beam, we need to ... [more] CAS2015-34 NLP2015-95
pp.69-74
VLD 2015-03-02
15:45
Okinawa Okinawa Seinen Kaikan Studies on Representation of Stacked Rectangular Dissections for 3D-LSI Floorplan
Kazufumi Kogai, Kunihiro Fujiyoshi (TUAT) VLD2014-159
A stacked-rectangular-dissection, which consists of several rectangular-dissections, each of which is a rectangular area... [more] VLD2014-159
pp.37-41
NLP, CAS 2014-10-16
09:15
Ehime Ehime University Improvement of Simulated Annealing Search Based on Tree Representations
Takaaki Banno, Kunihiro Fujiyoshi (TUAT) CAS2014-51 NLP2014-45
Simulated Annealing is a metaheuristic for the general optimization problem of locating a good approximation to the glob... [more] CAS2014-51 NLP2014-45
pp.1-6
VLD 2014-03-04
09:40
Okinawa Okinawa Seinen Kaikan An Effective Solution Space for Simulated Annealing
Hiroshi Tezuka, Kunihiro Fujiyoshi (TUAT) VLD2013-143
Simulated Annealing is a universal probabilistic metaheuristic for the general optimization problem of locating a good a... [more] VLD2013-143
pp.55-60
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-27
10:50
Kagoshima   Adjacent Common Centroid Placement for Analog IC Layout Design
Kenichiro Murotatsu, Kunihiro Fujiyoshi (TUAT) VLD2013-63 DC2013-29
To improve immunity against process gradients, common centroid constraints, in which every pair of capacitors should be... [more] VLD2013-63 DC2013-29
pp.13-18
MSS, CAS, IPSJ-AL [detail] 2013-11-06
15:50
Iwate   Simulated Annealing Method Based on (3n-4)-bit Representation of Rectangular Dissections
Kazufumi Kogai, Kunihiro Fujiyoshi (Tokyo Univ. of Agriculture and Tech.) CAS2013-60 MSS2013-39
(To be available after the conference date) [more] CAS2013-60 MSS2013-39
pp.55-60
SIP, CAS, MSS, VLD 2013-07-12
16:00
Kumamoto Kumamoto Univ. An Automatic Marking Method for Paper Patterns for Clothes by Simulated Annealing
Masayuki Harada, Tsuyoshi Ohshima, Kunihiro Fujiyoshi (TUAT) CAS2013-34 VLD2013-44 SIP2013-64 MSS2013-34
An automatic marking system, which places paper patterns of clothes automatically as much as possible density using the ... [more] CAS2013-34 VLD2013-44 SIP2013-64 MSS2013-34
pp.189-193
SIP, CAS, CS 2013-03-15
11:35
Yamagata Keio Univ. Tsuruoka Campus (Yamagata) A Branch-and-Bound Placement Method on Overlapped Printed Wiring Boards
Tetsuya Matsuura, Kunihiro Fujiyoshi (Tokyo Univ. of Agriculture and Tech.) CAS2012-124 SIP2012-155 CS2012-130
In undersized manufacturing products, some PWBs (Printed Wiring Boards) are installed with overlapping. The distance bet... [more] CAS2012-124 SIP2012-155 CS2012-130
pp.163-168
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
17:25
Kanagawa   An Improved Routing Method using Minimum Cost Flow for Routes with Target Wire Lengths
Kazuo Yamane, Kunihiro Fujiyoshi (TUAT) VLD2012-121 CPSY2012-70 RECONF2012-75
Due to the increase of operation frequency, influence of routing delays is increasing. So it is important to obtain the ... [more] VLD2012-121 CPSY2012-70 RECONF2012-75
pp.81-86
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-28
09:00
Fukuoka Centennial Hall Kyushu University School of Medicine On Handling Cell Placement with Adjacent Common Centroid Constraints for Analog IC Layout Design
Kunihiro Fujiyoshi, Keitaro Ue (TUAT) VLD2012-88 DC2012-54
(To be available after the conference date) [more] VLD2012-88 DC2012-54
pp.165-170
IPSJ-SLDM, VLD 2012-05-31
09:55
Fukuoka Kitakyushu International Conference Center A Placement Method on Overlapped Printed-Wiring-Boards
Tetsuya Matsuura, Kunihiro Fujiyoshi (TUAT) VLD2012-7
In undersized manufacturing products,
some PWBs (Printed Wiring Boards) are installed with overlapping.
The distance... [more]
VLD2012-7
pp.37-42
VLD 2010-09-28
10:00
Kyoto Kyoto Institute of Technology A Method of Analog IC Placement with Common Centroid Constraints
Keitaro Ue, Kunihiro Fujiyoshi (TUAT) VLD2010-48
Monolithic IC has a characteristic that absolute error of device parameter is large but relative variability is small.
... [more]
VLD2010-48
pp.37-42
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