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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2024-04-11 10:45 |
Kanagawa | (Primary: On-site, Secondary: Online) |
[Invited Lecture]
An SPN Strong PUF with SRAM-based Entropy Source Featuring Both 100-Bit Output Space and Modeling Attack Resilience Kunyang Liu (Kyoto Univ.), Yichen Tang (Lenovo), Shufan Xu, Kiichi Niitsu (Kyoto Univ.), Hirofumi Shinohara (Waseda Univ.)  ICD2024-2 |
Strong physically unclonable function (Strong PUF) is a hardware-security circuit that generates response outputs corres... [more] | ICD2024-2 p.7 |
| ICD | 2023-04-10 16:05 |
Kanagawa | (Primary: On-site, Secondary: Online) |
[Invited Lecture]
Strong PUF Using SRAM Weak PUF-Based Secret Substitution Layer for Edge-Device Security Applications Kunyang Liu, Hirofumi Shinohara (Waseda Univ.) ICD2023-7 |
Strong physically unclonable function (PUF) provides a promising solution for lightweight security applications aimed at... [more] | ICD2023-7 p.15 |
| HWS, ICD [detail] | 2021-10-19 11:40 |
Online | Online | Robustness Improvement by XORing Multiple Entropy Sources for True Random Number Generator
-- Stochastic Calculations of Mismatch-to-Noise Ratio -- Ruilin Zhang, Hirofumi Shinohara (Waseda Univ.) HWS2021-45 ICD2021-19 |
[more] | HWS2021-45 ICD2021-19 pp.23-25 |
| SDM, ICD, ITE-IST [detail] | 2021-08-18 14:50 |
Online | Online | [Invited Talk]
Latch Based Static and Dynamic Random Number Generators for Information Security Hirofumi Shinohara, Kunyang Liu, Ruilin Zhang, Xingyu Wang (Waseda Univ.) SDM2021-42 ICD2021-13 |
This paper describes latch-based TRNG and PUF with highly stable operations [more] | SDM2021-42 ICD2021-13 pp.64-67 |
| ICD | 2018-04-20 13:00 |
Tokyo | [Invited Talk]
Random Circuits for Information Security Hirofumi Shinohara (Waseda Univ.) ICD2018-11 |
[more] | ICD2018-11 p.45 |
|
| SDM, ICD, ITE-IST [detail] | 2017-08-01 09:45 |
Hokkaido | Hokkaido-Univ. Multimedia Education Bldg. | Parallel Programming of Non-volatile Power-up States of SRAM Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya (Univ. of Tokyo), Hirofumi Shinohara (Waseda Univ.), Masaharu Kobayashi, Toshiro Hiramoto (Univ. of Tokyo) SDM2017-38 ICD2017-26 |
A technique for using an ordinary SRAM array for programmable and readable non-volatile (NV) memory is proposed. Paralle... [more] | SDM2017-38 ICD2017-26 pp.49-54 |
| ICD | 2013-04-12 14:45 |
Ibaraki | Advanced Industrial Science and Technology (AIST) | [Invited Lecture]
A 13.8pJ/Access/Mbit SRAM with Charge Collector Circuits for Effective Use of Non-Selected Bit Line Charges Shinichi Moriwaki, Yasue Yamamoto, Toshikazu Suzuki (STARC), Atsushi Kawasumi (Toshiba), Shinji Miyano, Hirofumi Shinohara (STARC), Takayasu Sakurai (Univ. Tokyo) ICD2013-20 |
1Mb SRAM with charge collector circuits for effective use of non-selected bit line charges has been fabricated in 40nm t... [more] | ICD2013-20 pp.103-108 |
| ICD, SDM | 2012-08-02 11:25 |
Hokkaido | Sapporo Center for Gender Equality, Sapporo, Hokkaido | [Invited Talk]
Low Energy Dissipation Circuits with 0.5V Operation Voltage and Applications Hirofumi Shinohara (STARC) SDM2012-67 ICD2012-35 |
Extremely low voltage operation down to nearly or less than 0.5V has been gathering attention as a fundamental way to re... [more] | SDM2012-67 ICD2012-35 pp.23-28 |
| ICD | 2012-04-24 13:50 |
Iwate | Seion-so, Tsunagi Hot Spring (Iwate) | 0.4V SRAM with Bit Line Swing Suppression Charge Share Hierarchical Bit Line Scheme Shinichi Moriwaki, Atsushi Kawasumi (STARC), Toshikazu Suzuki (Panasonic), Yasue Yamamoto, Shinji Miyano, Hirofumi Shinohara (STARC), Takayasu Sakurai (Univ. of Tokyo) ICD2012-13 |
[more] | ICD2012-13 pp.67-71 |
| SDM, ICD | 2011-08-26 12:55 |
Toyama | Toyama kenminkaikan | [Invited Talk]
0.5V Extremely Low Power Circuits for Wireless Sensor Nodes with Energy Harvesting Makoto Takamiya, Koichi Ishida, Hiroshi Fuketa (Univ. of Tokyo), Masahiro Nomura, Hirofumi Shinohara (STARC), Takayasu Sakurai (Univ. of Tokyo) SDM2011-88 ICD2011-56 |
0.5V extremely low power circuits for wireless sensor nodes with energy harvesting are shown. Minimum operating voltage ... [more] | SDM2011-88 ICD2011-56 pp.87-92 |
| SDM, ICD | 2011-08-26 16:30 |
Toyama | Toyama kenminkaikan | Energy Efficiency Increase of Integer Unit Enabled by Contention-less Flip-Flops (CLFF) and Separated Supply Voltage between Flip-Flops and Combinational Logics Hiroshi Fuketa (Univ. of Tokyo), Koji Hirairi (STARC), Tadashi Yasufuku, Makoto Takamiya (Univ. of Tokyo), Masahiro Nomura, Hirofumi Shinohara (STARC), Takayasu Sakurai (Univ. of Tokyo) SDM2011-95 ICD2011-63 |
[more] | SDM2011-95 ICD2011-63 pp.127-132 |
| ICD | 2011-04-19 11:20 |
Hyogo | Kobe University Takigawa Memorial Hall | 0.5-V, 5.5-nsec Access Time, Bulk-CMOS 8T SRAM with Suspended Bit-Line Read Scheme Toshikazu Suzuki, Shinichi Moriwaki, Atsushi Kawasumi, Shinji Miyano, Hirofumi Shinohara (STARC) ICD2011-12 |
A low-voltage high-speed bulk-CMOS 8T SRAM is proposed. A novel 8-transistor (8T) memory cell with a complementary read ... [more] | ICD2011-12 pp.65-70 |
| ICD | 2010-04-22 10:50 |
Kanagawa | Shonan Institute of Tech. | A 45nm 0.6V Cross-Point 8T SRAM with Negative Biased Read/Write Assist Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Yasunobu Nakase, Hirofumi Shinohara (Renesas Electronics) ICD2010-3 |
We propose a new design solution for embedded SRAM macros with cross point 8T-SRAM for low operating voltage and power. ... [more] | ICD2010-3 pp.13-16 |
| ICD | 2008-12-12 16:35 |
Tokyo | Tokyo Inst. Tech., Ohokayama Campus, Kokusa-Kouryu-Kaikan | Post-Silicon Programmed Body-Biasing Platform Suppressing Device Variability in 45 nm CMOS Technology Issei Kashima, Hiroaki Suzuki, Masanori Kurimoto (Renesas Technology Corp), Tadao Yamanaka (Renesas Design), Hidehiro Takata (Renesas Technology Corp), Hiroshi Makino (Osaka Institute of Tech), Hirofumi Shinohara (Renesas Technology Corp) ICD2008-128 |
The Post-Silicon Programmed Body-Biasing Platform is proposed to suppress device variability in the 45-nm CMOS technolog... [more] | ICD2008-128 pp.137-142 |
| SDM [detail] | 2008-11-14 13:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
[Invited]Robust Design of Embedded SRAM on Deep-submicron Technology Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Hirofumi Shinohara (Renesas Technology Corp.) SDM2008-178 |
We develop high-density SRAM module in deep-submicron CMOS technology with the variation tolerant assist circuits agains... [more] | SDM2008-178 pp.55-60 |
| VLD | 2008-09-29 13:30 |
Ishikawa | [Invited Talk]
Phase-Adjustable Error Detection Flip-Flops with 2-Stage Hold Driven Optimization and Slack Based Grouping Scheme for Dynamic Voltage Scaling Masanori Kurimoto, Hiroaki Suzuki (Renesas Technology), Rei Akiyama, Tadao Yamanaka, Haruyuki Okuma (Renesas Design), Hidehiro Takata, Hirofumi Shinohara (Renesas Technology) VLD2008-47 |
[more] | VLD2008-47 pp.1-6 |
|
| ICD, SDM | 2007-08-24 16:05 |
Hokkaido | Kitami Institute of Technology | A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues Satoshi Ishikura, M. Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi (Matushita Electric Industrial), Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara (Renesas Technology), Hironori Akamatsu (Matushita Electric Industrial) SDM2007-168 ICD2007-96 |
We propose a new 2port SRAM with a 8T single-read-bitline (SRBL) memory cell for 45nm SOCs. Access time tends to be slow... [more] | SDM2007-168 ICD2007-96 pp.145-148 |
| ICD | 2007-04-13 09:40 |
Oita | [Invited Talk]
A 65 nm Embedded SRAM with Wafer Level Burn-In Mode, Leak-Bit Redundancy and E-trim Fuse for Known Good Die Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono (Renesas Technology), Yuji Oda (Shikino High-Tech), Susumu Imaoka (Renesas Design), Keiichi Usui (Daioh Electric), Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) ICD2007-11 |
We propose a Wafer Level Burn-In (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair s... [more] | ICD2007-11 pp.59-64 |
|
| ICD, SDM | 2006-08-18 12:05 |
Hokkaido | Hokkaido University | A 65 nm Ultra-High-Density Dual-port SRAM with 0.71um2 8T-cell for SoC Susumu Imaoka (Renesas Design), Koji Nii (Renesas Technology), Yasuhiro Masuda (Renesas Design), Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Motoshige Igarashi, Kazuo Tomita, Nobuo Tsuboi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) |
We propose a new access scheme of synchronous dual-port (DP) SRAM that minimizes area of 8T-DP-cell and keeps cell stabi... [more] | SDM2006-148 ICD2006-102 pp.133-136 |
| ICD, SDM | 2006-08-18 14:35 |
Hokkaido | Hokkaido University | A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits Makoto Yabuuchi, Shigeki Ohbayashi, Koji Nii, Yasumasa Tsukamoto (Renesas Technology), Susumu Imaoka (Renesas Design), Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Hiroshi Makino, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) |
[more] | SDM2006-151 ICD2006-105 pp.149-153 |
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